From 668650d58d61d9d170f3e5b5c1657ed1c3e2b34b Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Sat, 3 Dec 2016 17:29:44 -0800 Subject: Fix bugs with tbnz/tbz instructions. sim/aarch64 * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting. (dexTestBranchImmediate): Shift high bit of pos by 5 not 4. --- sim/aarch64/ChangeLog | 5 +++++ sim/aarch64/simulator.c | 6 +++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index d8eb000eb6..2eca54d510 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,3 +1,8 @@ +2016-12-03 Jim Wilson + + * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting. + (dexTestBranchImmediate): Shift high bit of pos by 5 not 4. + 2016-12-01 Jim Wilson * simulator.c (fsturs): Switch use of rn and st variables. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 4fa5dc1a59..34fd17d259 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -13353,7 +13353,7 @@ tbnz (sim_cpu *cpu, uint32_t pos, int32_t offset) unsigned rt = INSTR (4, 0); TRACE_DECODE (cpu, "emulated at line %d", __LINE__); - if (aarch64_get_reg_u64 (cpu, rt, NO_SP) & (1 << pos)) + if (aarch64_get_reg_u64 (cpu, rt, NO_SP) & (((uint64_t) 1) << pos)) aarch64_set_next_PC_by_offset (cpu, offset); } @@ -13364,7 +13364,7 @@ tbz (sim_cpu *cpu, uint32_t pos, int32_t offset) unsigned rt = INSTR (4, 0); TRACE_DECODE (cpu, "emulated at line %d", __LINE__); - if (!(aarch64_get_reg_u64 (cpu, rt, NO_SP) & (1 << pos))) + if (!(aarch64_get_reg_u64 (cpu, rt, NO_SP) & (((uint64_t) 1) << pos))) aarch64_set_next_PC_by_offset (cpu, offset); } @@ -13407,7 +13407,7 @@ dexTestBranchImmediate (sim_cpu *cpu) instr[18,5] = simm14 : signed offset counted in words instr[4,0] = uimm5 */ - uint32_t pos = ((INSTR (31, 31) << 4) | INSTR (23, 19)); + uint32_t pos = ((INSTR (31, 31) << 5) | INSTR (23, 19)); int32_t offset = simm32 (aarch64_get_instr (cpu), 18, 5) << 2; NYI_assert (30, 25, 0x1b); -- cgit v1.2.3