From b0252ef0c234de36b4affd07c6cfeebabff9268c Mon Sep 17 00:00:00 2001 From: meissner Date: Sun, 28 Oct 2018 04:05:15 +0000 Subject: checkpoint git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ibm/constant@265565 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog.meissner | 8 +++++ gcc/config/rs6000/rs6000.md | 74 ++++++++++++++++++++++----------------------- 2 files changed, 44 insertions(+), 38 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index ab07d9242eb..6fa742b49a3 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,11 @@ +2018-10-28 Michael Meissner + + * config/rs6000/rs6000.md (movsf_const_direct_move): Re-add + support for loading up GPRs. Add support for storing constants to + memory. + (movsf_const_direct_move_internal): Likewise. + (movsf_const_store): Delete, folded into the above functions. + 2018-10-27 Michael Meissner * config/rs6000/rs6000.md (movsf_const_direct_move): Delete diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index c7e100b909b..e176dc58416 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7285,58 +7285,56 @@ ;; SFmode since we are moving it to a VSX register. The power8's direct move ;; is too slow, so only do this on power9 systems and later. (define_insn_and_split "movsf_const_direct_move" - [(set (match_operand:SF 0 "gpc_reg_operand" "=wa") - (match_operand:SF 1 "easy_fp_direct_move_constant" "wG")) - (clobber (match_scratch:DI 2 "=b"))] + [(set (match_operand:SF 0 "nonimmediate_operand" "=wa,r,m") + (match_operand:SF 1 "easy_fp_direct_move_constant" "wG,wG,wG")) + (clobber (match_scratch:DI 2 "=b,b,b"))] "TARGET_P9_VECTOR && TARGET_POWERPC64" "#" "&& reload_completed" [(set (match_dup 2) (match_dup 3)) (set (match_dup 0) - (unspec:SF [(match_dup 2)] UNSPEC_SF_CONSTANT))] + (unspec:SF [(match_dup 2) + (match_dup 4)] UNSPEC_SF_CONSTANT))] { rtx src = operands[1]; - int endian = (WORDS_BIG_ENDIAN == 0); - long l2[2]; - HOST_WIDE_INT val; - REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (src), l2); - val = ((HOST_WIDE_INT)(unsigned long)l2[endian] << 32 - | ((HOST_WIDE_INT)(unsigned long)l2[1 - endian])); + if (which_alternative == 0) + { + int endian = (WORDS_BIG_ENDIAN == 0); + long l[2]; + HOST_WIDE_INT val; + REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (src), l); + val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 + | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); - operands[3] = GEN_INT (val); + operands[3] = GEN_INT (val); + operands[4] = const0_rtx; + } + else + { + long l; + REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (src), l); + operands[3] = GEN_INT (l); + operands[4] = const1_rtx; + } }) -;; Protect constant in DFmode format from being re-used in a GPR +;; Move SF constant to the final destination. Because SFmode in the VSX +;; registers is actually in the DFmode format, we need to identify whether the +;; constant loaded in the GPR will ultimately be moved to the VSX register or +;; kept in a GPR. (define_insn "*movsf_const_direct_move_internal" - [(set (match_operand:SF 0 "vsx_register_operand" "=wa") - (unspec:SF [(match_operand:DI 1 "int_reg_operand" "r")] + [(set (match_operand:SF 0 "nonimmediate_operand" "=wa,m,r,r") + (unspec:SF [(match_operand:DI 1 "int_reg_operand" "r,b,0,b") + (match_operand:DI 2 "const_0_to_1_operand" "O,n,n,n")] UNSPEC_SF_CONSTANT))] "TARGET_P9_VECTOR && TARGET_POWERPC64" - "mtvsrd %x0,%1" - [(set_attr "type" "mffgpr")]) - -; If we are just storing the SFmode constant, don't bother with direct move -(define_insn_and_split "*movsf_const_store" - [(set (match_operand:SF 0 "memory_operand" "=m") - (match_operand:SF 1 "easy_fp_direct_move_constant" "wG")) - (clobber (match_scratch:SI 2 "=b"))] - "TARGET_P9_VECTOR && TARGET_POWERPC64" - "#" - "&& reload_completed" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 4) - (match_dup 2))] -{ - rtx dest = operands[0]; - rtx src = operands[1]; - long l; - REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (src), l); - operands[3] = GEN_INT (l); - operands[4] = adjust_address (dest, SImode, 0); -}) - + "@ + mtvsrd %x0,%1 + stw%U0%X0 %1,%0 + # SF to same register + mr %0,%1" + [(set_attr "type" "mffgpr,store,*,*")]) ;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ ;; FMR MR MT%0 MF%1 NOP -- cgit v1.2.3