diff options
| author | jsm28 <jsm28@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-09-15 15:11:14 +0000 |
|---|---|---|
| committer | jsm28 <jsm28@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-09-15 15:11:14 +0000 |
| commit | bfb3552ac667f0ff446ead37833ad0216ffa74a6 (patch) | |
| tree | d54ba3ec8b70000ad108f64ea832717b8b404a26 | |
| parent | 1f8d5a3cc5050fde3770cce1ed62f1af91252088 (diff) | |
2005-09-15 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_load_tp): Copy result to pseudo.
* config/arm/arm.h (CLASS_LIKELY_SPILLED_P): Return 1 for RETURN_REG.
* config/arm/arm.md (load_tp_soft): Set conds attr.
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/csl-3_4_3-linux-branch@104309 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog.csl | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 17 | ||||
| -rw-r--r-- | gcc/config/arm/arm.h | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 1 |
4 files changed, 21 insertions, 8 deletions
diff --git a/gcc/ChangeLog.csl b/gcc/ChangeLog.csl index 21c2b7bb60d..5fcac30e5c8 100644 --- a/gcc/ChangeLog.csl +++ b/gcc/ChangeLog.csl @@ -1,3 +1,9 @@ +2005-09-15 Paul Brook <paul@codesourcery.com> + + * config/arm/arm.c (arm_load_tp): Copy result to pseudo. + * config/arm/arm.h (CLASS_LIKELY_SPILLED_P): Return 1 for RETURN_REG. + * config/arm/arm.md (load_tp_soft): Set conds attr. + 2005-09-15 Joseph Myers <joseph@codesourcery.com> * testsuite/gcc.dg/torture/pr19683-1.c: Remove XFAIL. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index ef6092d9a69..7e4aaed5c38 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3695,20 +3695,25 @@ get_tls_get_addr (void) static rtx arm_load_tp (rtx target) { + if (!target) + target = gen_reg_rtx (SImode); + if (TARGET_HARD_TP) { /* Can return in any reg. */ - if (!target) - target = gen_reg_rtx (SImode); - emit_insn (gen_load_tp_hard (target)); } else { /* Always returned in R0 */ - target = gen_rtx_REG (SImode, 0); - - emit_insn (gen_load_tp_soft (target)); + rtx tmp; + + /* Use a hard reg to avoid aborts in reload. See gcc.dg/opt-5.c */ + tmp = gen_rtx_REG (SImode, 0); + emit_insn (gen_load_tp_soft (tmp)); + /* Copy the result into a pseudo, otherwise other uses of r0 + (eg. setting up function arguments) may clobber the value. */ + emit_move_insn (target, tmp); } return target; } diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index d371659547d..eae40f14d92 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1264,9 +1264,10 @@ enum reg_class /* We need to define this for LO_REGS on thumb. Otherwise we can end up using r0-r4 for function arguments, r7 for the stack frame and don't have enough left over to do doubleword arithmetic. */ -#define CLASS_LIKELY_SPILLED_P(CLASS) \ +#define CLASS_LIKELY_SPILLED_P(CLASS) \ ((TARGET_THUMB && (CLASS) == LO_REGS) \ - || (CLASS) == CC_REG) + || (CLASS) == CC_REG \ + || (CLASS) == RETURN_REG) /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 871fc7202a8..890cda4f603 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -10277,6 +10277,7 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_SOFT_TP" "bl\\t__aeabi_read_tp\\t@ load_tp_soft" + [(set_attr "conds" "clob")] ) ;; Load the FPA co-processor patterns |