diff options
| author | H.J. Lu <hongjiu.lu@intel.com> | 2016-08-01 14:46:01 +0000 |
|---|---|---|
| committer | H.J. Lu <hongjiu.lu@intel.com> | 2016-08-01 14:46:01 +0000 |
| commit | c406f7b6cae173e0e91bbfb70d470bd7aed801a0 (patch) | |
| tree | 5781d70fc4d804f50fd6c8ef178c3367d78ec7ae | |
| parent | 9f484d572fb7f2db9dce28e7ac49ac3a3e92330a (diff) | |
Convert V1TImode register to TImode in debug insn
TImode register referenced in debug insn can be converted to V1TImode by
scalar to vector optimization. When converting a TImode store to V1TImode,
we need to check all debug insns on its use chain to convert the V1TImode
register to SUBREG TImode if source register is undefined.
gcc/
PR target/72748
* config/i386/i386.c (timode_scalar_chain::convert_insn): Call
fix_debug_reg_uses after changing source register mode to
V1TImode if source register is undefined.
gcc/testsuite/
PR target/72748
* gcc.target/i386/pr72748.c: New test.
git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@238956 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 6 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr72748.c | 27 |
4 files changed, 45 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e97f2ccc630..6302fc4d703 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2015-08-01 H.J. Lu <hongjiu.lu@intel.com> + + PR target/72748 + * config/i386/i386.c (timode_scalar_chain::convert_insn): Call + fix_debug_reg_uses after changing source register mode to + V1TImode if source register is undefined. + 2015-08-01 Alan Hayward <alan.hayward@arm.com> PR tree-optimization/71818 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 7c8bb17ff7c..93eaab10b91 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -3858,6 +3858,12 @@ timode_scalar_chain::convert_insn (rtx_insn *insn) switch (GET_CODE (src)) { case REG: + PUT_MODE (src, V1TImode); + /* Call fix_debug_reg_uses only if SRC is never defined. */ + if (!DF_REG_DEF_CHAIN (REGNO (src))) + fix_debug_reg_uses (src); + break; + case MEM: PUT_MODE (src, V1TImode); break; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8b65b3ee01f..d193e035c73 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-08-01 H.J. Lu <hongjiu.lu@intel.com> + + PR target/72748 + * gcc.target/i386/pr72748.c: New test. + 2015-08-01 Alan Hayward <alan.hayward@arm.com> PR tree-optimization/71818 diff --git a/gcc/testsuite/gcc.target/i386/pr72748.c b/gcc/testsuite/gcc.target/i386/pr72748.c new file mode 100644 index 00000000000..0d5e4f55309 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr72748.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -g" } */ + +volatile int a; +int c, d, e, f, g, h; + +int fn1 () +{ + int i; + for (; d;) + { + if (e) + break; + g = 0; + int j[4]; + for (h = 0; h < 4; h++) + g++; + for (; c < 2; c++) + { + e = j[g]; + i = j[0]; + f = 4; + } + f |= d; + } + return a; +} |