diff options
| author | Kelvin Nilsen <kelvin@gcc.gnu.org> | 2016-08-18 23:18:18 +0000 |
|---|---|---|
| committer | Kelvin Nilsen <kelvin@gcc.gnu.org> | 2016-08-18 23:18:18 +0000 |
| commit | 763807b931733029d979de44ce0430973d46aaf1 (patch) | |
| tree | fd8dcba91d473f6d68d777bedd7f8dd815b40df8 | |
| parent | b57547798dbc97a3a01fc6304842a8dc704131ae (diff) | |
compiles but not testing yetibm/rfc2467
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ibm/rfc2467@239600 138bc75d-0d04-0410-961f-82ee72b054a4
81 files changed, 2237 insertions, 1 deletions
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index 9123d969be9..2343c3024ae 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -409,6 +409,24 @@ #define vec_slv __builtin_vec_vslv #define vec_srv __builtin_vec_vsrv + +#ifdef _ARCH_PPC64 +#define vec_xl_len __builtin_vec_lxvl +#define vec_xst_len __builtin_vec_stxvl +#endif + +#define vec_cmpne __builtin_vec_vcmpne +#define vec_cmpnez __builtin_vec_vcmpnez +#define vec_all_ne __builtin_vec_vcmp_all_ne +#define vec_all_nez __builtin_vec_cmp_all_nez +#define vec_any_eq __builtin_vec_cmp_any_eq +#define vec_any_eqz __builtin_vec_cmp_any_eqz + +#define vec_cntlz_lsbb __builtin_vec_vclzlsbb +#define vec_cnttz_lsbb __builtin_vec_vctzlsbb + +#define vec_xlx __builtin_vec_vextulx +#define vec_xrx __builtin_vec_vexturx #endif /* Predicates. diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index fef3fd4b496..e4aec3575c3 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -799,6 +799,14 @@ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ +#define BU_P9V_VSX_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_vsx_" NAME, /* NAME */ \ + RS6000_BTM_P9_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + #define BU_P9V_OVERLOAD_1(ENUM, NAME) \ RS6000_BUILTIN_1 (P9V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ @@ -1799,6 +1807,63 @@ BU_P9V_OVERLOAD_2 (VADUB, "vadub") BU_P9V_OVERLOAD_2 (VADUH, "vaduh") BU_P9V_OVERLOAD_2 (VADUW, "vaduw") +/* 2 argument vector functions added in ISA 3.0 (power9). */ +BU_P9V_VSX_2 (LXVL, "lxvl", CONST, lxvl) +BU_P9V_VSX_2 (STXVL, "stxvl", CONST, stxvl) + +BU_P9V_AV_2 (VCMPNEB, "vcmpneb", CONST, vcmpneb) +BU_P9V_AV_2 (VCMPNEB_AT, "vcmpb_all_ne", CONST, vcmpneb_at) +BU_P9V_AV_2 (VCMPNEB_NAF, "vcmpb_any_eq", CONST, vcmpneb_naf) + +BU_P9V_AV_2 (VCMPNEH, "vcmpneh", CONST, vcmpneh) +BU_P9V_AV_2 (VCMPNEH_AT, "vcmph_all_ne", CONST, vcmpneh_at) +BU_P9V_AV_2 (VCMPNEH_NAF, "vcmph_any_eq", CONST, vcmpneh_naf) + +BU_P9V_AV_2 (VCMPNEW, "vcmpnew", CONST, vcmpnew) +BU_P9V_AV_2 (VCMPNEW_AT, "vcmpw_all_ne", CONST, vcmpnew_at) +BU_P9V_AV_2 (VCMPNEW_NAF, "vcmpw_any_eq", CONST, vcmpnew_naf) + +BU_P9V_AV_2 (VCMPNEZB, "vcmpnezb", CONST, vcmpnezb) +BU_P9V_AV_2 (VCMPNEZB_AT, "vcmpzb_all_ne", CONST, vcmpnezb_at) +BU_P9V_AV_2 (VCMPNEZB_NAF, "vcmpb_any_eqz", CONST, vcmpnezb_naf) + +BU_P9V_AV_2 (VCMPNEZH, "vcmpnezh", CONST, vcmpnezh) +BU_P9V_AV_2 (VCMPNEZH_AT, "vcmpzh_all_ne", CONST, vcmpnezh_at) +BU_P9V_AV_2 (VCMPNEZH_NAF, "vcmph_any_eqz", CONST, vcmpnezh_naf) + +BU_P9V_AV_2 (VCMPNEZW, "vcmpnezw", CONST, vcmpnezw) +BU_P9V_AV_2 (VCMPNEZW_AT, "vcmpzw_all_ne", CONST, vcmpnezw_at) +BU_P9V_AV_2 (VCMPNEZW_NAF, "vcmpw_any_eqz", CONST, vcmpnezw_naf) + +BU_P9V_AV_2 (VEXTUBLX, "vextublx", CONST, vextublx) +BU_P9V_AV_2 (VEXTUBRX, "vextubrx", CONST, vextubrx) +BU_P9V_AV_2 (VEXTUHLX, "vextuhlx", CONST, vextuhlx) +BU_P9V_AV_2 (VEXTUHRX, "vextuhrx", CONST, vextuhrx) +BU_P9V_AV_2 (VEXTUWLX, "vextuwlx", CONST, vextuwlx) +BU_P9V_AV_2 (VEXTUWRX, "vextuwrx", CONST, vextuwrx) + +/* 1 argument vector functions added in ISA 3.0 (power9). */ +BU_P9V_AV_1 (VCLZLSBB, "vclzlsbb", CONST, vclzlsbb) +BU_P9V_AV_1 (VCTZLSBB, "vctzlsbb", CONST, vctzlsbb) + +/* ISA 3.0 Vector scalar overloaded 2 argument functions */ +BU_P9V_OVERLOAD_2 (LXVL, "lxvl") +BU_P9V_OVERLOAD_2 (STXVL, "stxvl") + +BU_P9V_OVERLOAD_2 (VCMPNE, "vcmpne") +BU_P9V_OVERLOAD_2 (VCMPNEZ, "vcmpnez") +BU_P9V_OVERLOAD_2 (VCMPNE_AT, "vcmp_all_ne") +BU_P9V_OVERLOAD_2 (VCMPNEZ_AT, "vcmp_all_nez") +BU_P9V_OVERLOAD_2 (VCMPNE_NAF, "vcmp_any_eq") +BU_P9V_OVERLOAD_2 (VCMPNEZ_NAF, "vcmp_any_eqz") + +BU_P9V_OVERLOAD_2 (VEXTULX, "vextulx") +BU_P9V_OVERLOAD_2 (VEXTURX, "vexturx") + +/* ISA 3.0 Vector scalar overloaded 1 argument functions */ +BU_P9V_OVERLOAD_1 (VCLZLSBB, "vclzlsbb") +BU_P9V_OVERLOAD_1 (VCTZLSBB, "vctzlsbb") + /* 2 argument extended divide functions added in ISA 2.06. */ BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si) diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 2a60262f034..72546adb351 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -4302,6 +4302,306 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, + RS6000_BTI_V16QI, ~RS6000_BTI_INTQI, + RS6000_BTI_unsigned_long_long, 0 }, + { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, + RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, + RS6000_BTI_unsigned_long_long, 0 }, + + { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, + RS6000_BTI_V4SI, ~RS6000_BTI_INTSI, + RS6000_BTI_unsigned_long_long, 0 }, + { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, + RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI, + RS6000_BTI_unsigned_long_long, 0 }, + + { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, + RS6000_BTI_V1TI, ~RS6000_BTI_INTTI, + RS6000_BTI_unsigned_long_long, 0 }, + { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, + RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI, + RS6000_BTI_unsigned_long_long, 0 }, + + { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, + RS6000_BTI_V2DI, ~RS6000_BTI_INTDI, + RS6000_BTI_unsigned_long_long, 0 }, + { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, + RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_UINTDI, + RS6000_BTI_unsigned_long_long, 0 }, + + { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, + RS6000_BTI_V2DF, ~RS6000_BTI_double, + RS6000_BTI_unsigned_long_long, 0 }, + { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, + RS6000_BTI_V4SF, ~RS6000_BTI_float, + RS6000_BTI_unsigned_long_long, 0 }, + /* at an appropriate future time, add support for the + RS6000_BTI_Float16 (exact name to be determined) type here */ + + { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, + RS6000_BTI_V16QI, ~RS6000_BTI_INTQI, + RS6000_BTI_unsigned_long_long, 0 }, + { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, + RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, + RS6000_BTI_unsigned_long_long, 0 }, + + { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, + RS6000_BTI_V4SI, ~RS6000_BTI_INTSI, + RS6000_BTI_unsigned_long_long, 0 }, + { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, + RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI, + RS6000_BTI_unsigned_long_long, 0 }, + + { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, + RS6000_BTI_V1TI, ~RS6000_BTI_INTTI, + RS6000_BTI_unsigned_long_long, 0 }, + { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, + RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI, + RS6000_BTI_unsigned_long_long, 0 }, + + { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, + RS6000_BTI_V2DI, ~RS6000_BTI_INTDI, + RS6000_BTI_unsigned_long_long, 0 }, + { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, + RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_UINTDI, + RS6000_BTI_unsigned_long_long, 0 }, + + { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, + RS6000_BTI_V2DF, ~RS6000_BTI_double, + RS6000_BTI_unsigned_long_long, 0 }, + { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, + RS6000_BTI_V4SF, ~RS6000_BTI_float, + RS6000_BTI_unsigned_long_long, 0 }, + /* at an appropriate future time, add support for the + RS6000_BTI_Float16 (exact name to be determined) type here */ + + { P9V_BUILTIN_VEC_VCMPNE, P9V_BUILTIN_VCMPNEB, + RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, + RS6000_BTI_V16QI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE, P9V_BUILTIN_VCMPNEB, + RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNE, P9V_BUILTIN_VCMPNEH, + RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, + RS6000_BTI_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE, P9V_BUILTIN_VCMPNEH, + RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNE, P9V_BUILTIN_VCMPNEW, + RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, + RS6000_BTI_V4SI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE, P9V_BUILTIN_VCMPNEW, + RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNEZ, P9V_BUILTIN_VCMPNEZB, + RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, + RS6000_BTI_V16QI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ, P9V_BUILTIN_VCMPNEZB, + RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNEZ, P9V_BUILTIN_VCMPNEZH, + RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, + RS6000_BTI_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ, P9V_BUILTIN_VCMPNEZH, + RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNEZ, P9V_BUILTIN_VCMPNEZW, + RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, + RS6000_BTI_V4SI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ, P9V_BUILTIN_VCMPNEZW, + RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNE_AT, P9V_BUILTIN_VCMPNEB_AT, + RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, + RS6000_BTI_bool_V16QI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE_AT, P9V_BUILTIN_VCMPNEB_AT, + RS6000_BTI_INTSI, RS6000_BTI_V16QI, + RS6000_BTI_V16QI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE_AT, P9V_BUILTIN_VCMPNEB_AT, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNE_AT, P9V_BUILTIN_VCMPNEH_AT, + RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, + RS6000_BTI_bool_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE_AT, P9V_BUILTIN_VCMPNEH_AT, + RS6000_BTI_INTSI, RS6000_BTI_V8HI, + RS6000_BTI_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE_AT, P9V_BUILTIN_VCMPNEH_AT, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE_AT, P9V_BUILTIN_VCMPNEH_AT, + RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, + RS6000_BTI_pixel_V8HI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNE_AT, P9V_BUILTIN_VCMPNEW_AT, + RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, + RS6000_BTI_bool_V4SI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE_AT, P9V_BUILTIN_VCMPNEW_AT, + RS6000_BTI_INTSI, RS6000_BTI_V4SI, + RS6000_BTI_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE_AT, P9V_BUILTIN_VCMPNEW_AT, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNEZ_AT, P9V_BUILTIN_VCMPNEZB_AT, + RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, + RS6000_BTI_bool_V16QI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ_AT, P9V_BUILTIN_VCMPNEZB_AT, + RS6000_BTI_INTSI, RS6000_BTI_V16QI, + RS6000_BTI_V16QI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ_AT, P9V_BUILTIN_VCMPNEZB_AT, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNEZ_AT, P9V_BUILTIN_VCMPNEZH_AT, + RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, + RS6000_BTI_bool_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ_AT, P9V_BUILTIN_VCMPNEZH_AT, + RS6000_BTI_INTSI, RS6000_BTI_V8HI, + RS6000_BTI_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ_AT, P9V_BUILTIN_VCMPNEZH_AT, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ_AT, P9V_BUILTIN_VCMPNEZH_AT, + RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, + RS6000_BTI_pixel_V8HI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNEZ_AT, P9V_BUILTIN_VCMPNEZW_AT, + RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, + RS6000_BTI_bool_V4SI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ_AT, P9V_BUILTIN_VCMPNEZW_AT, + RS6000_BTI_INTSI, RS6000_BTI_V4SI, + RS6000_BTI_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ_AT, P9V_BUILTIN_VCMPNEZW_AT, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNE_NAF, P9V_BUILTIN_VCMPNEB_NAF, + RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, + RS6000_BTI_bool_V16QI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE_NAF, P9V_BUILTIN_VCMPNEB_NAF, + RS6000_BTI_INTSI, RS6000_BTI_V16QI, + RS6000_BTI_V16QI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE_NAF, P9V_BUILTIN_VCMPNEB_NAF, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNE_NAF, P9V_BUILTIN_VCMPNEH_NAF, + RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, + RS6000_BTI_bool_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE_NAF, P9V_BUILTIN_VCMPNEH_NAF, + RS6000_BTI_INTSI, RS6000_BTI_V8HI, + RS6000_BTI_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE_NAF, P9V_BUILTIN_VCMPNEH_NAF, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE_NAF, P9V_BUILTIN_VCMPNEH_NAF, + RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, + RS6000_BTI_pixel_V8HI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNE_NAF, P9V_BUILTIN_VCMPNEW_NAF, + RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, + RS6000_BTI_bool_V4SI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE_NAF, P9V_BUILTIN_VCMPNEW_NAF, + RS6000_BTI_INTSI, RS6000_BTI_V4SI, + RS6000_BTI_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNE_NAF, P9V_BUILTIN_VCMPNEW_NAF, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNEZ_NAF, P9V_BUILTIN_VCMPNEZB_NAF, + RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, + RS6000_BTI_bool_V16QI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ_NAF, P9V_BUILTIN_VCMPNEZB_NAF, + RS6000_BTI_INTSI, RS6000_BTI_V16QI, + RS6000_BTI_V16QI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ_NAF, P9V_BUILTIN_VCMPNEZB_NAF, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNEZ_NAF, P9V_BUILTIN_VCMPNEZH_NAF, + RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, + RS6000_BTI_bool_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ_NAF, P9V_BUILTIN_VCMPNEZH_NAF, + RS6000_BTI_INTSI, RS6000_BTI_V8HI, + RS6000_BTI_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ_NAF, P9V_BUILTIN_VCMPNEZH_NAF, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ_NAF, P9V_BUILTIN_VCMPNEZH_NAF, + RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, + RS6000_BTI_pixel_V8HI, 0 }, + + { P9V_BUILTIN_VEC_VCMPNEZ_NAF, P9V_BUILTIN_VCMPNEZW_NAF, + RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, + RS6000_BTI_bool_V4SI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ_NAF, P9V_BUILTIN_VCMPNEZW_NAF, + RS6000_BTI_INTSI, RS6000_BTI_V4SI, + RS6000_BTI_V8HI, 0 }, + { P9V_BUILTIN_VEC_VCMPNEZ_NAF, P9V_BUILTIN_VCMPNEZW_NAF, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + + { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB, + RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 }, + { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + + { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB, + RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 }, + { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + + { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX, + RS6000_BTI_INTQI, RS6000_BTI_UINTSI, + RS6000_BTI_V16QI, 0 }, + { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX, + RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, + RS6000_BTI_unsigned_V16QI, 0 }, + + { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX, + RS6000_BTI_INTHI, RS6000_BTI_UINTSI, + RS6000_BTI_V8HI, 0 }, + { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX, + RS6000_BTI_UINTHI, RS6000_BTI_UINTSI, + RS6000_BTI_unsigned_V8HI, 0 }, + + { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, + RS6000_BTI_V4SI, 0 }, + { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX, + RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, + RS6000_BTI_unsigned_V4SI, 0 }, + + { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX, + RS6000_BTI_INTQI, RS6000_BTI_UINTSI, + RS6000_BTI_V16QI, 0 }, + { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX, + RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, + RS6000_BTI_unsigned_V16QI, 0 }, + + { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX, + RS6000_BTI_INTHI, RS6000_BTI_UINTSI, + RS6000_BTI_V8HI, 0 }, + { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX, + RS6000_BTI_UINTHI, RS6000_BTI_UINTSI, + RS6000_BTI_unsigned_V8HI, 0 }, + + { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, + RS6000_BTI_V4SI, 0 }, + { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX, + RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index b66b1affd7c..c9f910736ae 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -311,6 +311,34 @@ UNSPEC_P9_MEMORY UNSPEC_VSX_VSLO UNSPEC_VSX_EXTRACT + UNSPEC_LXVL + UNSPEC_STXVL + UNSPEC_VCMPNEB + UNSPEC_VCMPNEB_AT + UNSPEC_VCMPNEB_AF + UNSPEC_VCMPNEZB + UNSPEC_VCMPNEZB_AT + UNSPEC_VCMPNEZB_AF + UNSPEC_VCMPNEH + UNSPEC_VCMPNEH_AT + UNSPEC_VCMPNEH_AF + UNSPEC_VCMPNEZH + UNSPEC_VCMPNEZH_AT + UNSPEC_VCMPNEZH_AF + UNSPEC_VCMPNEW + UNSPEC_VCMPNEW_AT + UNSPEC_VCMPNEW_AF + UNSPEC_VCMPNEZW + UNSPEC_VCMPNEZW_AT + UNSPEC_VCMPNEZW_AF + UNSPEC_VCLZLSBB + UNSPEC_VCTZLSBB + UNSPEC_VEXTUBLX + UNSPEC_VEXTUBRX + UNSPEC_VEXTUHLX + UNSPEC_VEXTUHRX + UNSPEC_VEXTUWLX + UNSPEC_VEXTUWRX ]) ;; VSX moves @@ -2859,3 +2887,483 @@ mfvsrd %0,%x1 stxsi<wd>x %x1,%y0" [(set_attr "type" "mffgpr,fpstore")]) + +;; ISA 3.0 String Operations (VSU) Support + +;; Load VSX Vector with Length +(define_expand "lxvl" + [(set (match_dup 3) + (match_operand:DI 2 "register_operand" "r")) + (set (match_operand:V16QI 0 "vsx_register_operand" "=wa") + (unspec:V16QI + [(match_operand:DI 1 "gpc_reg_operand" "b") + (match_dup 3)] + UNSPEC_LXVL))] + "TARGET_P9_VECTOR && TARGET_64BIT" +{ + operands[3] = gen_reg_rtx (DImode); +}) + +(define_insn "*lxvl" + [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") + (unspec:V16QI + [(match_operand:DI 1 "gpc_reg_operand" "b") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_LXVL))] + "TARGET_P9_VECTOR && TARGET_64BIT" + "sldi %2,%2, 56\; lxvl %x0,%1,%2" + [(set_attr "length" "8") + (set_attr "type" "vecload")]) + +;; Store VSX Vector with Length +(define_expand "stxvl" + [(set (match_dup 3) + (match_operand:DI 2 "register_operand" "r")) + (set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b")) + (unspec:V16QI + [(match_operand:V16QI 0 "vsx_register_operand" "wa") + (match_dup 3)] + UNSPEC_STXVL))] + "TARGET_P9_VECTOR && TARGET_64BIT" +{ + operands[3] = gen_reg_rtx (DImode); +}) + +(define_insn "*stxvl" + [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b")) + (unspec:V16QI + [(match_operand:V16QI 0 "vsx_register_operand" "wa") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_STXVL))] + "TARGET_P9_VECTOR && TARGET_64BIT" + "sldi %2,%2\;stxvl %x0,%1,%2" + [(set_attr "length" "8") + (set_attr "type" "vecstore")]) + +;; Vector Compare Not Equal Byte +(define_insn "vcmpneb" + [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "altivec_register_operand" "v") + (match_operand:V16QI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEB))] + "TARGET_P9_VECTOR" + "vcmpneb %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +;; Vector Compare Not Equal Byte All True +;; (Within CR field 6, all true, which means "none of the comparisons +;; matched", corresponds to the "gt" flag being set. All false, which +;; means "all of the bytes matched", corresponds to the "eq" flag +;; being set.) +(define_expand "vcmpneb_at" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:SI [(match_operand:V16QI 1 "altivec_register_operand" "v") + (match_operand:V16QI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEB) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (gt:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P9_VECTOR") + +;; Vector Compare Not Equal Byte Not All False (aka any equal) +;; (Within CR field 6, all true, which means "none of the comparisons +;; matched", corresponds to the "gt" flag being set. All false, which +;; means "all of the bytes matched", corresponds to the "eq" flag +;; being set.) +(define_expand "vcmpneb_naf" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:SI [(match_operand:V16QI 1 "altivec_register_operand" "v") + (match_operand:V16QI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEB) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (ne:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P9_VECTOR") +;; above, kelvin is making a guess on how to complement the value of the +;; the test condition. originally, the test condition was (eq:SI) but I +;; want the complement of that value. let's see if it generates the +;; intended code. + +(define_insn "*vcmpneb_alltest" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") + (compare:CCFP + (unspec:SI [(match_operand:V16QI 1 "altivec_register_operand" "wa") + (match_operand:V16QI 2 "altivec_register_operand" "wa")] + UNSPEC_VCMPNEB) + (match_operand:SI 3 "zero_constant" "j")))] + "TARGET_P9_VECTOR" + "vcmpneb. %0,%1,%2" + [(set_attr "type" "fpcompare")]) + +;; Vector Compare Not Equal or Zero Byte +(define_insn "vcmpnezb" + [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") + (unspec:V16QI + [(match_operand:V16QI 1 "altivec_register_operand" "v") + (match_operand:V16QI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEZB))] + "TARGET_P9_VECTOR" + "vcmpnezb %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +;; Vector Compare Not Equal or Zero Byte All True +;; (Within CR field 6, all true, which means "none of the comparisons +;; matched", corresponds to the "gt" flag being set. All false, which +;; means "all of the bytes matched", corresponds to the "eq" flag +;; being set.) +(define_expand "vcmpnezb_at" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:SI [(match_operand:V16QI 1 "altivec_register_operand" "v") + (match_operand:V16QI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEZB) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (gt:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P9_VECTOR") + +;; Vector Compare Not Equal or Zero Byte Not All False +;; (aka any equal and not zero) +;; (Within CR field 6, all true, which means "none of the comparisons +;; matched", corresponds to the "gt" flag being set. All false, which +;; means "all of the bytes matched", corresponds to the "eq" flag +;; being set.) +(define_expand "vcmpnezb_naf" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:SI [(match_operand:V16QI 1 "altivec_register_operand" "v") + (match_operand:V16QI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEZB) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (ne:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P9_VECTOR") + +(define_insn "*vcmpnezb_alltest" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") + (compare:CCFP + (unspec:SI [(match_operand:V16QI 1 "altivec_register_operand" "v") + (match_operand:V16QI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEZB) + (match_operand:SI 3 "zero_constant" "j")))] + "TARGET_P9_VECTOR" + "vcmpnezb. %0,%1,%2" + [(set_attr "type" "fpcompare")]) + +;; Vector Compare Not Equal Half Word +(define_insn "vcmpneh" + [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "altivec_register_operand" "v") + (match_operand:V8HI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEH))] + "TARGET_P9_VECTOR" + "vcmpneh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +;; Vector Compare Not Equal Half Word All True +;; (Within CR field 6, all true, which means "none of the comparisons +;; matched", corresponds to the "gt" flag being set. All false, which +;; means "all of the bytes matched", corresponds to the "eq" flag +;; being set.) +(define_expand "vcmpneh_at" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:SI [(match_operand:V8HI 1 "altivec_register_operand" "v") + (match_operand:V8HI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEH) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (gt:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P9_VECTOR") + +;; Vector Compare Not Equal Not All False (aka any equal) +;; (Within CR field 6, all true, which means "none of the comparisons +;; matched", corresponds to the "gt" flag being set. All false, which +;; means "all of the bytes matched", corresponds to the "eq" flag +;; being set.) +(define_expand "vcmpneh_naf" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:SI [(match_operand:V8HI 1 "altivec_register_operand" "v") + (match_operand:V8HI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEH) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (ne:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P9_VECTOR") + +(define_insn "*vcmpneh_alltest" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") + (compare:CCFP + (unspec:SI [(match_operand:V8HI 1 "altivec_register_operand" "v") + (match_operand:V8HI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEH) + (match_operand:SI 3 "zero_constant" "j")))] + "TARGET_P9_VECTOR" + "vcmpneh. %0,%1,%2" + [(set_attr "type" "fpcompare")]) + +;; Vector Compare Not Equal or Zero Half Word +(define_insn "vcmpnezh" + [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "altivec_register_operand" "v") + (match_operand:V8HI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEZH))] + "TARGET_P9_VECTOR" + "vcmpnezh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +;; Vector Compare Not Equal or Zero Half Word All True +;; (Within CR field 6, all true, which means "none of the comparisons +;; matched", corresponds to the "gt" flag being set. All false, which +;; means "all of the bytes matched", corresponds to the "eq" flag +;; being set.) +(define_expand "vcmpnezh_at" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:SI [(match_operand:V8HI 1 "altivec_register_operand" "v") + (match_operand:V8HI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEZH) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (gt:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P9_VECTOR") + +;; Vector Compare Not Equal or Zero Half Word Not All False +;; (aka any equal and not zero) +;; (Within CR field 6, all true, which means "none of the comparisons +;; matched", corresponds to the "gt" flag being set. All false, which +;; means "all of the bytes matched", corresponds to the "eq" flag +;; being set.) +(define_expand "vcmpnezh_naf" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:SI + [(match_operand:V8HI 1 "altivec_register_operand" "v") + (match_operand:V8HI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEZH) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (ne:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P9_VECTOR") + +(define_insn "*vcmpnezh_alltest" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") + (compare:CCFP + (unspec:SI [(match_operand:V8HI 1 "altivec_register_operand" "v") + (match_operand:V8HI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEZH) + (match_operand:SI 3 "zero_constant" "j")))] + "TARGET_P9_VECTOR" + "vcmpnezh. %0,%1,%2" + [(set_attr "type" "fpcompare")]) + +;; Vector Compare Not Equal Word +(define_insn "vcmpnew" + [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") + (unspec:V4SI + [(match_operand:V4SI 1 "altivec_register_operand" "v") + (match_operand:V4SI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEH))] + "TARGET_P9_VECTOR" + "vcmpnew %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +;; Vector Compare Not Equal Word All True +;; (Within CR field 6, all true, which means "none of the comparisons +;; matched", corresponds to the "gt" flag being set. All false, which +;; means "all of the bytes matched", corresponds to the "eq" flag +;; being set.) +(define_expand "vcmpnew_at" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:SI + [(match_operand:V4SI 1 "altivec_register_operand" "v") + (match_operand:V4SI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEW) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (gt:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P9_VECTOR") + +;; Vector Compare Not Equal Word Not All False (aka any equal) +;; (Within CR field 6, all true, which means "none of the comparisons +;; matched", corresponds to the "gt" flag being set. All false, which +;; means "all of the bytes matched", corresponds to the "eq" flag +;; being set.) +(define_expand "vcmpnew_naf" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:SI [(match_operand:V4SI 1 "altivec_register_operand" "v") + (match_operand:V4SI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEW) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (ne:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P9_VECTOR") + +(define_insn "*vcmpnew_alltest" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") + (compare:CCFP + (unspec:SI [(match_operand:V4SI 1 "altivec_register_operand" "v") + (match_operand:V4SI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEW) + (match_operand:SI 3 "zero_constant" "j")))] + "TARGET_P9_VECTOR" + "vcmpnew. %0,%1,%2" + [(set_attr "type" "fpcompare")]) + +;; Vector Compare Not Equal or Zero Word +(define_insn "vcmpnezw" + [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "altivec_register_operand" "v") + (match_operand:V4SI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEZW))] + "TARGET_P9_VECTOR" + "vcmpnezw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +;; Vector Compare Not Equal or Zero Word All True +;; (Within CR field 6, all true, which means "none of the comparisons +;; matched", corresponds to the "gt" flag being set. All false, which +;; means "all of the bytes matched", corresponds to the "eq" flag +;; being set.) +(define_expand "vcmpnezw_at" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:SI + [(match_operand:V4SI 1 "altivec_register_operand" "v") + (match_operand:V4SI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEZW) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (gt:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P9_VECTOR") + +;; Vector Compare Not Equal or Zero Byte Not All False +;; (aka any equal and not zero) +;; (Within CR field 6, all true, which means "none of the comparisons +;; matched", corresponds to the "gt" flag being set. All false, which +;; means "all of the bytes matched", corresponds to the "eq" flag +;; being set.) +(define_expand "vcmpnezw_naf" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:SI [(match_operand:V4SI 1 "altivec_register_operand" "v") + (match_operand:V4SI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEZW) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (ne:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P9_VECTOR") + +(define_insn "*cmpnezw_alltest" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") + (compare:CCFP + (unspec:SI [(match_operand:V4SI 1 "altivec_register_operand" "v") + (match_operand:V4SI 2 "altivec_register_operand" "v")] + UNSPEC_VCMPNEZW) + (match_operand:SI 3 "zero_constant" "j")))] + "TARGET_P9_VECTOR" + "vcmpnezw. %0,%1,%2" + [(set_attr "type" "fpcompare")]) + +;; Vector Count Leading Zero Least-Significant Bits Byte +(define_insn "vclzlsbb" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI + [(match_operand:V16QI 1 "altivec_register_operand" "v")] + UNSPEC_VCLZLSBB))] + "TARGET_P9_VECTOR" + "vclzlsbb %0,%1" + [(set_attr "type" "vecsimple")]) + +;; Vector Count Trailing Zero Least-Significant Bits Byte +(define_insn "vctzlsbb" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI + [(match_operand:V16QI 1 "altivec_register_operand" "v")] + UNSPEC_VCTZLSBB))] + "TARGET_P9_VECTOR" + "vctzlsbb %0,%1" + [(set_attr "type" "vecsimple")]) + +;; Vector Extract Unsigned Byte Left-Indexed +(define_insn "vextublx" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI + [(match_operand:SI 1 "register_operand" "r") + (match_operand:V16QI 2 "altivec_register_operand" "v")] + UNSPEC_VEXTUBLX))] + "TARGET_P9_VECTOR" + "vextublx %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +;; Vector Extract Unsigned Byte Right-Indexed +(define_insn "vextubrx" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI + [(match_operand:SI 1 "register_operand" "r") + (match_operand:V16QI 2 "altivec_register_operand" "v")] + UNSPEC_VEXTUBLX))] + "TARGET_P9_VECTOR" + "vextubrx %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +;; Vector Extract Unsigned Half Word Left-Indexed +(define_insn "vextuhlx" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI + [(match_operand:SI 1 "register_operand" "r") + (match_operand:V16QI 2 "altivec_register_operand" "v")] + UNSPEC_VEXTUBLX))] + "TARGET_P9_VECTOR" + "vextuhlx %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +;; Vector Extract Unsigned Half Word Right-Indexed +(define_insn "vextuhrx" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI + [(match_operand:SI 1 "register_operand" "r") + (match_operand:V16QI 2 "altivec_register_operand" "v")] + UNSPEC_VEXTUBLX))] + "TARGET_P9_VECTOR" + "vextuhrx %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +;; Vector Extract Unsigned Word Left-Indexed +(define_insn "vextuwlx" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI + [(match_operand:SI 1 "register_operand" "r") + (match_operand:V16QI 2 "altivec_register_operand" "v")] + UNSPEC_VEXTUBLX))] + "TARGET_P9_VECTOR" + "vextuwlx %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +;; Vector Extract Unsigned Word Right-Indexed +(define_insn "vextuwrx" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI + [(match_operand:SI 1 "register_operand" "r") + (match_operand:V16QI 2 "altivec_register_operand" "v")] + UNSPEC_VEXTUBLX))] + "TARGET_P9_VECTOR" + "vextuwrx %0,%1,%2" + [(set_attr "type" "vecsimple")]) diff --git a/gcc/gencodes.c b/gcc/gencodes.c index 3b0fc5ce9f8..56b9ecfa10f 100644 --- a/gcc/gencodes.c +++ b/gcc/gencodes.c @@ -27,6 +27,10 @@ along with GCC; see the file COPYING3. If not see #include "rtl.h" #include "errors.h" #include "gensupport.h" +#undef KELVIN_DEBUG +#ifdef KELVIN_DEBUG +#include "print-rtl.h" +#endif static void gen_insn (md_rtx_info *info) @@ -72,6 +76,16 @@ enum insn_code {\n\ md_rtx_info info; while (read_md_rtx (&info)) +#ifdef KELVIN_DEBUG + { + fprintf (stderr, "Reading machine description, name is: %s\n", + XSTR (info.def, 0)); + fprintf (stderr, "The C string definition is: %s\n", + XSTR (info.def, 2)); + /* + print_rtl (stderr, info.def); + */ +#endif switch (GET_CODE (info.def)) { case DEFINE_INSN: @@ -82,7 +96,9 @@ enum insn_code {\n\ default: break; } - +#ifdef KELVIN_DEBUG + } +#endif printf ("\n};\n\ \n\ const unsigned int NUM_INSN_CODES = %d;\n\ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-0.c new file mode 100644 index 00000000000..120cb9b4d96 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-0.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int +test_all_not_equal (vector bool char *arg1_p, vector bool char *arg2_p) +{ + vector bool char arg_1 = *arg1_p; + vector bool char arg_2 = *arg2_p; + + return vec_all_ne (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneb." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-1.c new file mode 100644 index 00000000000..d05b1239303 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed char +test_all_not_equal (vector signed char *arg1_p, vector signed char *arg2_p) +{ + vector signed char arg_1 = *arg1_p; + vector signed char arg_2 = *arg2_p; + + return vec_all_ne (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneb." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-2.c new file mode 100644 index 00000000000..3cd735c3029 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned char +test_all_not_equal (vector unsigned char *arg1_p, vector unsigned char *arg2_p) +{ + vector unsigned char arg_1 = *arg1_p; + vector unsigned char arg_2 = *arg2_p; + + return vec_all_ne (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneb." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-3.c new file mode 100644 index 00000000000..1c7d950c298 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-3.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed short +test_all_not_equal (vector signed short *arg1_p, vector signed short *arg2_p) +{ + vector signed short arg_1 = *arg1_p; + vector signed short arg_2 = *arg2_p; + + return vec_all_ne (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneh." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-4.c new file mode 100644 index 00000000000..e58426d90f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned short +test_all_not_equal (vector unsigned short *arg1_p, + vector unsigned short *arg2_p) +{ + vector unsigned short arg_1 = *arg1_p; + vector unsigned short arg_2 = *arg2_p; + + return vec_all_ne (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneh." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-5.c new file mode 100644 index 00000000000..d5c34edac06 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-5.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed int +test_all_not_equal (vector signed int *arg1_p, vector signed int *arg2_p) +{ + vector signed int arg_1 = *arg1_p; + vector signed int arg_2 = *arg2_p; + + return vec_all_ne (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnew." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-6.c new file mode 100644 index 00000000000..6cd61aa9219 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-6.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned int +test_all_not_equal (vector unsigned int *arg1_p, vector unsigned int *arg2_p) +{ + vector unsigned int arg_1 = *arg1_p; + vector unsigned int arg_2 = *arg2_p; + + return vec_all_ne (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnew." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-7.c new file mode 100644 index 00000000000..29333285de5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-7.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +vector unsigned short +test_all_not_equal (vector unsigned short *arg1_p, vector unsigned short *arg2_p) +{ + vector unsigned short arg_1 = *arg1_p; + vector unsigned short arg_2 = *arg2_p; + + return vec_all_ne (arg_1, arg_2); /* {dg-error "Builtin function __builtin_vec_all_ne requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-0.c new file mode 100644 index 00000000000..7c76404912f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-0.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int +test_all_not_equal_and_not_zero (vector bool char *arg1_p, + vector bool char *arg2_p) +{ + vector bool char arg_1 = *arg1_p; + vector bool char arg_2 = *arg2_p; + + return vec_all_nez (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneb." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-1.c new file mode 100644 index 00000000000..2e1ec7868dc --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed char +test_all_not_equal_and_not_zero (vector signed char *arg1_p, + vector signed char *arg2_p) +{ + vector signed char arg_1 = *arg1_p; + vector signed char arg_2 = *arg2_p; + + return vec_all_nez (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneb." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-2.c new file mode 100644 index 00000000000..0001eb700b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned char +test_all_not_equal_and_not_zero (vector unsigned char *arg1_p, + vector unsigned char *arg2_p) +{ + vector unsigned char arg_1 = *arg1_p; + vector unsigned char arg_2 = *arg2_p; + + return vec_all_nez (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneb." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-3.c new file mode 100644 index 00000000000..2d055b429ea --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed short +test_all_not_equal_and_not_zero (vector signed short *arg1_p, + vector signed short *arg2_p) +{ + vector signed short arg_1 = *arg1_p; + vector signed short arg_2 = *arg2_p; + + return vec_all_nez (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneh." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-4.c new file mode 100644 index 00000000000..367541fee91 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned short +test_all_not_equal_and_not_zero (vector unsigned short *arg1_p, + vector unsigned short *arg2_p) +{ + vector unsigned short arg_1 = *arg1_p; + vector unsigned short arg_2 = *arg2_p; + + return vec_all_nez (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneh." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-5.c new file mode 100644 index 00000000000..3fe17e207cf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-5.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed int +test_all_not_equal_and_not_zero (vector signed int *arg1_p, + vector signed int *arg2_p) +{ + vector signed int arg_1 = *arg1_p; + vector signed int arg_2 = *arg2_p; + + return vec_all_nez (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnew." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-6.c new file mode 100644 index 00000000000..1328d52336c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-6.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned int +test_all_not_equal_and_not_zero (vector unsigned int *arg1_p, + vector unsigned int *arg2_p) +{ + vector unsigned int arg_1 = *arg1_p; + vector unsigned int arg_2 = *arg2_p; + + return vec_all_nez (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnew." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c new file mode 100644 index 00000000000..d36e53944b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +vector unsigned short +test_all_not_equal_and_not_zero (vector unsigned short *arg1_p, vector unsigned short *arg2_p) +{ + vector unsigned short arg_1 = *arg1_p; + vector unsigned short arg_2 = *arg2_p; + + return vec_all_nez (arg_1, arg_2); /* {dg-error "Builtin function __builtin_vec_all_nez requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-0.c new file mode 100644 index 00000000000..c3528e02ace --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-0.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int +test_any_equal (vector bool char *arg1_p, vector bool char *arg2_p) +{ + vector bool char arg_1 = *arg1_p; + vector bool char arg_2 = *arg2_p; + + return vec_any_eq (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneb." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-1.c new file mode 100644 index 00000000000..d791629b4a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed char +test_any_equal (vector signed char *arg1_p, vector signed char *arg2_p) +{ + vector signed char arg_1 = *arg1_p; + vector signed char arg_2 = *arg2_p; + + return vec_any_eq (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneb." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-2.c new file mode 100644 index 00000000000..7e4f1f33afb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned char +test_any_equal (vector unsigned char *arg1_p, vector unsigned char *arg2_p) +{ + vector unsigned char arg_1 = *arg1_p; + vector unsigned char arg_2 = *arg2_p; + + return vec_any_eq (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneb." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-3.c new file mode 100644 index 00000000000..48970dbc6ac --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-3.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed short +test_any_equal (vector signed short *arg1_p, vector signed short *arg2_p) +{ + vector signed short arg_1 = *arg1_p; + vector signed short arg_2 = *arg2_p; + + return vec_any_eq (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneh." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-4.c new file mode 100644 index 00000000000..33bd8c2317f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned short +test_any_equal (vector unsigned short *arg1_p, + vector unsigned short *arg2_p) +{ + vector unsigned short arg_1 = *arg1_p; + vector unsigned short arg_2 = *arg2_p; + + return vec_any_eq (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneh." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-5.c new file mode 100644 index 00000000000..652915b15bc --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-5.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed int +test_any_equal (vector signed int *arg1_p, vector signed int *arg2_p) +{ + vector signed int arg_1 = *arg1_p; + vector signed int arg_2 = *arg2_p; + + return vec_any_eq (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnew." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-6.c new file mode 100644 index 00000000000..d55b4839b3c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-6.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned int +test_any_equal (vector unsigned int *arg1_p, vector unsigned int *arg2_p) +{ + vector unsigned int arg_1 = *arg1_p; + vector unsigned int arg_2 = *arg2_p; + + return vec_any_eq (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnew." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c new file mode 100644 index 00000000000..ec02cbe94d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +vector unsigned short +test_any_equal (vector unsigned short *arg1_p, vector unsigned short *arg2_p) +{ + vector unsigned short arg_1 = *arg1_p; + vector unsigned short arg_2 = *arg2_p; + + return vec_any_eq (arg_1, arg_2); /* {dg-error "Builtin function __builtin_vec_any_eq requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-0.c new file mode 100644 index 00000000000..3d43d187efe --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-0.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int +test_any_equal_or_zero (vector bool char *arg1_p, vector bool char *arg2_p) +{ + vector bool char arg_1 = *arg1_p; + vector bool char arg_2 = *arg2_p; + + return vec_any_eqz (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnezb." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-1.c new file mode 100644 index 00000000000..6ececb7dd82 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed char +test_any_equal_or_zero (vector signed char *arg1_p, vector signed char *arg2_p) +{ + vector signed char arg_1 = *arg1_p; + vector signed char arg_2 = *arg2_p; + + return vec_any_eqz (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneb." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-2.c new file mode 100644 index 00000000000..41bc8c11003 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned char +test_any_equal_or_zero (vector unsigned char *arg1_p, + vector unsigned char *arg2_p) +{ + vector unsigned char arg_1 = *arg1_p; + vector unsigned char arg_2 = *arg2_p; + + return vec_any_eqz (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneb." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-3.c new file mode 100644 index 00000000000..0d07bda176f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed short +test_any_equal_or_zero (vector signed short *arg1_p, + vector signed short *arg2_p) +{ + vector signed short arg_1 = *arg1_p; + vector signed short arg_2 = *arg2_p; + + return vec_any_eqz (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneh." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-4.c new file mode 100644 index 00000000000..47dfff4041d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned short +test_any_equal_or_zero (vector unsigned short *arg1_p, + vector unsigned short *arg2_p) +{ + vector unsigned short arg_1 = *arg1_p; + vector unsigned short arg_2 = *arg2_p; + + return vec_any_eqz (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneh." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-5.c new file mode 100644 index 00000000000..605ff097be5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-5.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed int +test_any_equal_or_zero (vector signed int *arg1_p, vector signed int *arg2_p) +{ + vector signed int arg_1 = *arg1_p; + vector signed int arg_2 = *arg2_p; + + return vec_any_eqz (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnew." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-6.c new file mode 100644 index 00000000000..1410b51fd67 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-6.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned int +test_any_equal_or_zero (vector unsigned int *arg1_p, + vector unsigned int *arg2_p) +{ + vector unsigned int arg_1 = *arg1_p; + vector unsigned int arg_2 = *arg2_p; + + return vec_any_eqz (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnew." } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c new file mode 100644 index 00000000000..8e036e3e2c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector bool char +fetch_data (vector bool char *arg1_p, vector bool char *arg2_p) +{ + vector bool char arg_1 = *arg1_p; + vector bool char arg_2 = *arg2_p; + + return vec_cmpne (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneb" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c new file mode 100644 index 00000000000..9a4daf0bc8c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed char +fetch_data (vector signed char *arg1_p, vector signed char *arg2_p) +{ + vector signed char arg_1 = *arg1_p; + vector signed char arg_2 = *arg2_p; + + return vec_cmpne (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneb" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c new file mode 100644 index 00000000000..bcfd40cd5d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned char +fetch_data (vector unsigned char *arg1_p, vector unsigned char *arg2_p) +{ + vector unsigned char arg_1 = *arg1_p; + vector unsigned char arg_2 = *arg2_p; + + return vec_cmpne (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneb" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c new file mode 100644 index 00000000000..d057cb25709 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed short +fetch_data (vector signed short *arg1_p, vector signed short *arg2_p) +{ + vector signed short arg_1 = *arg1_p; + vector signed short arg_2 = *arg2_p; + + return vec_cmpne (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneh" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c new file mode 100644 index 00000000000..25de6465b33 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned short +fetch_data (vector unsigned short *arg1_p, vector unsigned short *arg2_p) +{ + vector unsigned short arg_1 = *arg1_p; + vector unsigned short arg_2 = *arg2_p; + + return vec_cmpne (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpneh" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c new file mode 100644 index 00000000000..6d9a263ed13 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed int +fetch_data (vector signed int *arg1_p, vector signed int *arg2_p) +{ + vector signed int arg_1 = *arg1_p; + vector signed int arg_2 = *arg2_p; + + return vec_cmpne (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnew" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c new file mode 100644 index 00000000000..d0948d32b31 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned int +fetch_data (vector unsigned int *arg1_p, vector unsigned int *arg2_p) +{ + vector unsigned int arg_1 = *arg1_p; + vector unsigned int arg_2 = *arg2_p; + + return vec_cmpne (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnew" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-7.c new file mode 100644 index 00000000000..73a61c5143a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-7.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +vector unsigned short +fetch_data (vector unsigned short *arg1_p, vector unsigned short *arg2_p) +{ + vector unsigned short arg_1 = *arg1_p; + vector unsigned short arg_2 = *arg2_p; + + return vec_cmpne (arg_1, arg_2); /* {dg-error "Builtin function __builtin_vec_cmpne requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-0.c new file mode 100644 index 00000000000..53104eb8d31 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-0.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector bool char +fetch_data (vector bool char *arg1_p, vector bool char *arg2_p) +{ + vector bool char arg_1 = *arg1_p; + vector bool char arg_2 = *arg2_p; + + return vec_cmpnez (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnezb" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-1.c new file mode 100644 index 00000000000..0d3ca730152 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed char +fetch_data (vector signed char *arg1_p, vector signed char *arg2_p) +{ + vector signed char arg_1 = *arg1_p; + vector signed char arg_2 = *arg2_p; + + return vec_cmpnez (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnezb" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-2.c new file mode 100644 index 00000000000..109b167c82c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned char +fetch_data (vector unsigned char *arg1_p, vector unsigned char *arg2_p) +{ + vector unsigned char arg_1 = *arg1_p; + vector unsigned char arg_2 = *arg2_p; + + return vec_cmpnez (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnezb" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-3.c new file mode 100644 index 00000000000..3da4f9b22af --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-3.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed short +fetch_data (vector signed short *arg1_p, vector signed short *arg2_p) +{ + vector signed short arg_1 = *arg1_p; + vector signed short arg_2 = *arg2_p; + + return vec_cmpnez (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnezh" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-4.c new file mode 100644 index 00000000000..342422b0583 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-4.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned short +fetch_data (vector unsigned short *arg1_p, vector unsigned short *arg2_p) +{ + vector unsigned short arg_1 = *arg1_p; + vector unsigned short arg_2 = *arg2_p; + + return vec_cmpnez (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnezh" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-5.c new file mode 100644 index 00000000000..c1b04e7e1bb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-5.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector signed int +fetch_data (vector signed int *arg1_p, vector signed int *arg2_p) +{ + vector signed int arg_1 = *arg1_p; + vector signed int arg_2 = *arg2_p; + + return vec_cmpnez (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnezw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-6.c new file mode 100644 index 00000000000..dccc8ccd6fb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-6.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +vector unsigned int +fetch_data (vector unsigned int *arg1_p, vector unsigned int *arg2_p) +{ + vector unsigned int arg_1 = *arg1_p; + vector unsigned int arg_2 = *arg2_p; + + return vec_cmpnez (arg_1, arg_2); +} + +/* { dg-final { scan-assembler "vcmpnezw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c new file mode 100644 index 00000000000..70ef02f2bf7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +vector unsigned int +fetch_data (vector unsigned int *arg1_p, vector unsigned int *arg2_p) +{ + vector unsigned int arg_1 = *arg1_p; + vector unsigned int arg_2 = *arg2_p; + + return vec_cmpnez (arg_1, arg_2); /* {dg-error "Builtin function __builtin_vec_cmpnez requies" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-0.c new file mode 100644 index 00000000000..89bb400e49f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-0.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector signed char +fetch_data (signed char *address, size_t length) +{ + return vec_xl_len (address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "lxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-1.c new file mode 100644 index 00000000000..8c7f000e535 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector unsigned char +fetch_data (unsigned char *address, size_t length) +{ + return vec_xl_len (address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "lxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-10.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-10.c new file mode 100644 index 00000000000..24a123f5d75 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-10.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector double +fetch_data (double *address, size_t length) +{ + return vec_xl_len (address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "lxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-11.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-11.c new file mode 100644 index 00000000000..2c76cb11ed5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-11.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector float +fetch_data (float *address, size_t length) +{ + return vec_xl_len (address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "lxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-12.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-12.c new file mode 100644 index 00000000000..36042995d69 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-12.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +/* The vec_xl_len() function is not available on power8 configurations. */ + +#include <altivec.h> + +__vector float +fetch_data (float *address, size_t length) +{ + return vec_xl_len (address, length); /* {dg-error "Builtin function __builtin_vec_xl requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c new file mode 100644 index 00000000000..00545d63284 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target ip32 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +/* This test only runs on 32-bit configurations, where a compiler + error should be issued because this built-in function is not + available on 32-bit configurations. */ + +__vector float +fetch_data (float *address, size_t length) +{ + return vec_xl_len (address, length); /* {dg-error "Builtin function __builtin_vec_lxvl not supported in this configuration" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-2.c new file mode 100644 index 00000000000..5e36f0ea5f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector signed int +fetch_data (signed int *address, size_t length) +{ + __vector float source = *p; + + return vec_xl_len (address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "lxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-3.c new file mode 100644 index 00000000000..1d52d89a96c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-3.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector unsigned int +fetch_data (unsigned int *address, size_t length) +{ + return vec_xl_len (address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "lxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-4.c new file mode 100644 index 00000000000..7d08ad4ec00 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-4.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector signed __int128 +fetch_data (signed __int128 *address, size_t length) +{ + return vec_xl_len (address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "lxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-5.c new file mode 100644 index 00000000000..7c0c5a9bec9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-5.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector unsigned __int128 +fetch_data (unsigned __int128 *address, size_t length) +{ + return vec_xl_len (address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "lxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-6.c new file mode 100644 index 00000000000..ad21dd5eac6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-6.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector signed long long +fetch_data (signed long long *address, size_t length) +{ + return vec_xl_len (address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "lxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-7.c new file mode 100644 index 00000000000..59f2c078636 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-7.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector unsigned long long +fetch_data (unsigned long long *address, size_t length) +{ + return vec_xl_len (address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "lxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-8.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-8.c new file mode 100644 index 00000000000..f1d43ff2ebd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-8.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector signed short +fetch_data (signed short *address, size_t length) +{ + return vec_xl_len (address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "lxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-9.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-9.c new file mode 100644 index 00000000000..37bd039b9ad --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-9.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector unsigned short +fetch_data (unsigned short *address, size_t length) +{ + return vec_xl_len (address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "lxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-0.c new file mode 100644 index 00000000000..ead558d4759 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-0.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +void +store_data (vector signed char *datap, signed char *address, size_t length) +{ + vector signed char data = *datap; + + vec_xst_len (data, address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "stxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-1.c new file mode 100644 index 00000000000..5afcb1a37ae --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +void +store_data (vector unsigned char *datap, unsigned char *address, size_t length) +{ + vector unsigned char data = *datap; + + vec_xst_len (data, address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "stxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-10.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-10.c new file mode 100644 index 00000000000..1e8e25e7457 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-10.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +void +store_data (vector double *datap, souble *address, + size_t length) +{ + vector double data = *datap; + + vec_xst_len (data, address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "stxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-11.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-11.c new file mode 100644 index 00000000000..1e8e25e7457 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-11.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +void +store_data (vector double *datap, souble *address, + size_t length) +{ + vector double data = *datap; + + vec_xst_len (data, address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "stxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c new file mode 100644 index 00000000000..2c49eabd614 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +/* The vec_xst_len() function is not available on power8 configurations. */ + +void +store_data (vector double *datap, souble *address, + size_t length) +{ + vector double data = *datap; + + vec_xst_len (data, address, length); /* {dg-error "Builtin function __builtin_vec_xst requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-13.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-13.c new file mode 100644 index 00000000000..41d8ca889bc --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-13.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target ip32 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +/* This test only runs on 32-bit configurations, where a compiler + error should be issued because this built-in function is not + available on 32-bit configurations. */ + +void +store_data (vector double *datap, souble *address, + size_t length) +{ + vector double data = *datap; + + vec_xst_len (data, address, length); /* {dg-error "Builtin function __builtin_vec_xst not supported in this configuration" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-2.c new file mode 100644 index 00000000000..4538d983edb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +void +store_data (vector signed int *datap, signed int *address, size_t length) +{ + vector signed int data = *datap; + + vec_xst_len (data, address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "stxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-3.c new file mode 100644 index 00000000000..6fee81b7b22 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +void +store_data (vector unsigned int *datap, unsigned int *address, size_t length) +{ + vector unsigned int data = *datap; + + vec_xst_len (data, address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "stxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-4.c new file mode 100644 index 00000000000..6fee81b7b22 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +void +store_data (vector unsigned int *datap, unsigned int *address, size_t length) +{ + vector unsigned int data = *datap; + + vec_xst_len (data, address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "stxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-5.c new file mode 100644 index 00000000000..cf40bbaf90b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-5.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +void +store_data (vector unsigned __int128 *datap, unsigned __int128 *address, + size_t length) +{ + vector unsigned __int128 data = *datap; + + vec_xst_len (data, address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "stxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-6.c new file mode 100644 index 00000000000..01349a78ccd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-6.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +void +store_data (vector signed long long *datap, signed long long *address, + size_t length) +{ + vector signed long long data = *datap; + + vec_xst_len (data, address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "stxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-7.c new file mode 100644 index 00000000000..831f9fd3255 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-7.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +void +store_data (vector unsigned long long *datap, unsigned long long *address, + size_t length) +{ + vector unsigned long long data = *datap; + + vec_xst_len (data, address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "stxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-8.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-8.c new file mode 100644 index 00000000000..a945b031c77 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-8.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +void +store_data (vector signed short *datap, signed short *address, + size_t length) +{ + vector signed short data = *datap; + + vec_xst_len (data, address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "stxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-9.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-9.c new file mode 100644 index 00000000000..de5a8b3d892 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-9.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +void +store_data (vector unsigned short *datap, unsigned short *address, + size_t length) +{ + vector unsigned short data = *datap; + + vec_xst_len (data, address, length); +} + +/* { dg-final { scan-assembler "sldi" } } */ +/* { dg-final { scan-assembler "stxvl" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vsu.exp b/gcc/testsuite/gcc.target/powerpc/vsu/vsu.exp new file mode 100644 index 00000000000..fcce6961a11 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vsu.exp @@ -0,0 +1,40 @@ +# Copyright (C) 2014-2016 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# Exit immediately if this isn't a PowerPC target or if the target is aix. +if { (![istarget powerpc*-*-*] && ![istarget rs6000-*-*]) + || [istarget "powerpc*-*-aix*"] } then { + return +} + +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Load support procs. +load_lib gcc-dg.exp +load_lib torture-options.exp + +# Initialize. +dg-init + +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.c*]] "" $DEFAULT_CFLAGS + +# All done. +dg-finish |