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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2016-05-31 22:08:36 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@linux.vnet.ibm.com> | 2016-05-31 22:08:36 +0000 |
| commit | c747d667ea0ad67c976201a8c5aa65858cacef1b (patch) | |
| tree | f581950e2266a7f02c45da3a3b19f5d303b99942 | |
| parent | 2a8d3433fe5de989d051370024c875fc0b3b45bc (diff) | |
Backport vector d-form support
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ibm/power9-gcc6@236957 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/dform-3.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/powerpc/dform-3.c b/gcc/testsuite/gcc.target/powerpc/dform-3.c new file mode 100644 index 00000000000..b1c481fbf6d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dform-3.c @@ -0,0 +1,39 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */ + +#ifndef TYPE +#define TYPE vector double +#endif + +struct foo { + TYPE a, b, c, d; +}; + +/* Test whether ISA 3.0 vector d-form instructions are implemented. */ +void +add (struct foo *p) +{ + p->b = p->c + p->d; +} + +/* Make sure we don't use direct moves to get stuff into GPR registers. */ +void +gpr (struct foo *p) +{ + TYPE x = p->c; + + __asm__ (" # reg = %0" : "+r" (x)); + + p->b = x; +} + +/* { dg-final { scan-assembler "lxv " } } */ +/* { dg-final { scan-assembler "stxv " } } */ +/* { dg-final { scan-assembler-not "lxvx " } } */ +/* { dg-final { scan-assembler-not "stxvx " } } */ +/* { dg-final { scan-assembler-not "mfvsrd " } } */ +/* { dg-final { scan-assembler-not "mfvsrld " } } */ +/* { dg-final { scan-assembler "l\[dq\] " } } */ +/* { dg-final { scan-assembler "st\[dq\] " } } */ |