compiles for legal code

git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ibm/kelvin-rfc2463@235457 138bc75d-0d04-0410-961f-82ee72b054a4

3 files changed, 172 insertions, 5 deletions

diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index a631ff5fd9e..34de0f3eb18 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -318,8 +318,12 @@
    UNSPEC_DXEX
    UNSPEC_DIEX
    UNSPEC_DSCLI
+   UNSPEC_DTSTSFI
    UNSPEC_DSCRI])
 
+(define_code_iterator DFP_TEST [eq lt gt unordered])
+
+
 (define_mode_iterator D64_D128 [DD TD])
 
 (define_mode_attr dfp_suffix [(DD "")
@@ -351,6 +355,46 @@
   "dxex<dfp_suffix> %0,%1"
   [(set_attr "type" "fp")])
 
+(define_expand "bcdtstsfi_<code>_<mode>"
+  [(parallel [(set
+	       (reg:CCFP 74)
+	       (compare:CCFP
+	        (unspec:D64_D128 
+		 [(match_operand:SI 1 "const_int_operand" "i")
+		  (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
+	 	 UNSPEC_DTSTSFI)
+		(match_dup 3)))
+	       (clobber (match_scratch:CCFP 4 ""))])
+   (set (match_operand:SI 0 "register_operand" "")
+   	(BCD_TEST:SI (reg:CCFP 74) (const_int 0)))
+  ]
+  "TARGET_P9_VECTOR"
+{
+  operands[3] = CONST0_RTX (SImode);
+})
+
+(define_insn "*dfp_sgnfcnc_<mode>"
+  [(set (reg:CCFP 74)
+        (compare:CCFP
+	 (unspec:D64_D128 [(match_operand:SI 1 "" "i")
+	 	           (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
+          UNSPEC_DTSTSFI)
+	 (match_operand:SI 3 "zero_constant" "j")))
+   (clobber (match_scratch:CCFP 0 "=y"))]
+  "TARGET_P9_VECTOR"
+  {
+    if (UINTVAL (operands[1]) > 63)
+    {
+      /* If immediate operand is greater than 63, it will behave as if
+       * the value had been 63.  The code generator does not support 
+       * immediate operand values greater than 63. */
+      return "dtstfiq<dfp_suffix> %0,63,%2";
+    }
+    else
+      return "dtstfiq<dfp_suffix> %0,%1,%2";
+  }
+  [(set_attr "type" "fp")])
+
 (define_insn "dfp_diex_<mode>"
   [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
 	(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 267f6c17d43..12d304174be 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -656,6 +656,14 @@
 /* Miscellaneous builtins for instructions added in ISA 3.0.  These
    instructions don't require either the DFP or VSX options, just the basic 
    ISA 3.0 enablement since they operate on general purpose registers.  */
+#define BU_P9_MISC_0(ENUM, NAME, ATTR, ICODE)                      \
+  RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_" NAME,			/* NAME */	\
+		    RS6000_BTM_MODULO,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_SPECIAL),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
 #define BU_P9_MISC_1(ENUM, NAME, ATTR, ICODE)				\
   RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM,		/* ENUM */	\
 		    "__builtin_" NAME,			/* NAME */	\
@@ -677,17 +685,62 @@
 		     | RS6000_BTC_SPECIAL),				\
 		    CODE_FOR_ ## ICODE)			/* ICODE */
 
-/* Miscellaneous builtins for instructions added in ISA 3.0.  These
-   instructions don't require either the DFP or VSX options, just the basic 
-   ISA 3.0 enablement since they operate on general purpose registers.  */
-#define BU_P9_MISC_0(ENUM, NAME, ATTR, ICODE)                      \
+/* Miscellaneous builtins for decimal floating point instructions
+   added in ISA 3.0.  These instructions don't require either the VSX
+   options, just the basic ISA 3.0 enablement since they operate on
+   general purpose registers.  */ 
+#define BU_P9_DFP_MISC_0(ENUM, NAME, ATTR, ICODE)			\
   RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM,		/* ENUM */	\
 		    "__builtin_" NAME,			/* NAME */	\
-		    RS6000_BTM_MODULO,			/* MASK */	\
+		    (RS6000_BTM_MODULO 					\
+		     | RS6000_BTM_DFP),			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_SPECIAL),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_P9_DFP_MISC_1(ENUM, NAME, ATTR, ICODE)			\
+  RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_" NAME,			/* NAME */	\
+		    (RS6000_BTM_MODULO 					\
+		     | RS6000_BTM_DFP),			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_SPECIAL),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_P9_DFP_MISC_2(ENUM, NAME, ATTR, ICODE)			\
+  RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_" NAME,			/* NAME */	\
+		    (RS6000_BTM_MODULO 					\
+		     | RS6000_BTM_DFP),			/* MASK */	\
 		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
 		     | RS6000_BTC_SPECIAL),				\
 		    CODE_FOR_ ## ICODE)			/* ICODE */
 
+/* Decimal floating point overloaded functions added in ISA 3.0 */
+#define BU_P9_DFP_OVERLOAD_1(ENUM, NAME)				\
+  RS6000_BUILTIN_1 (P9_BUILTIN_DFP_ ## ENUM,		/* ENUM */	\
+		    "__builtin_dfp_" NAME,		/* NAME */	\
+		    RS6000_BTM_MODULO,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_UNARY),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+#define BU_P9_DFP_OVERLOAD_2(ENUM, NAME)				\
+  RS6000_BUILTIN_2 (P9_BUILTIN_DFP_ ## ENUM,		/* ENUM */	\
+		    "__builtin_dfp_" NAME,		/* NAME */	\
+		    RS6000_BTM_MODULO,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_BINARY),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+#define BU_P9_DFP_OVERLOAD_3(ENUM, NAME)				\
+  RS6000_BUILTIN_3 (P9_BUILTIN_DFP_ ## ENUM,		/* ENUM */	\
+		    "__builtin_dfp_" NAME,		/* NAME */	\
+		    RS6000_BTM_MODULO,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_TERNARY),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
 /* ISA 3.0 (power9) vector convenience macros.  */
 /* For the instructions that are encoded as altivec instructions use
    __builtin_altivec_ as the builtin name.  */
@@ -1760,6 +1813,36 @@ BU_P9_MISC_0 (DARN_32,		"darn_32", 		MISC, darn_32)
 BU_P9_64BIT_MISC_0 (DARN_RAW,	"darn_raw", 		MISC, darn_raw)
 BU_P9_64BIT_MISC_0 (DARN,	"darn",			MISC, darn)
 
+/* 2 argument BCD functions added in ISA 3.0.  */
+BU_P9_DFP_MISC_2 (BCD_TSTSFI_LT_DD, "dtstsfi_lt_dd", CONST, bcdtstsfi_lt_dd)
+BU_P9_DFP_MISC_2 (BCD_TSTSFI_LT_TD, "dtstsfi_lt_td", CONST, bcdtstsfi_lt_td)
+
+BU_P9_DFP_MISC_2 (BCD_TSTSFI_EQ_DD, "dtstsfi_eq_dd", CONST, bcdtstsfi_eq_dd)
+BU_P9_DFP_MISC_2 (BCD_TSTSFI_EQ_TD, "dtstsfi_eq_td", CONST, bcdtstsfi_eq_td)
+
+BU_P9_DFP_MISC_2 (BCD_TSTSFI_GT_DD, "dtstsfi_gt_dd", CONST, bcdtstsfi_gt_dd)
+BU_P9_DFP_MISC_2 (BCD_TSTSFI_GT_TD, "dtstsfi_gt_td", CONST, bcdtstsfi_gt_td)
+
+BU_P9_DFP_MISC_2 (BCD_TSTSFI_OV_DD, "dtstsfi_ov_dd", CONST, bcdtstsfi_unordered_dd)
+BU_P9_DFP_MISC_2 (BCD_TSTSFI_OV_TD, "dtstsfi_ov_td", CONST, bcdtstsfi_unordered_td)
+
+/* 2 argument overloaded BCD functions added in ISA 3.0.  */
+BU_P9_DFP_OVERLOAD_2 (BCD_TSTSFI_LT,	"dtstsfi_lt")
+BU_P9_DFP_OVERLOAD_2 (BCD_TSTSFI_LT_DD,	"dtstsfi_lt_dd")
+BU_P9_DFP_OVERLOAD_2 (BCD_TSTSFI_LT_TD,	"dtstsfi_lt_td")
+
+BU_P9_DFP_OVERLOAD_2 (BCD_TSTSFI_EQ,	"dtstsfi_eq")
+BU_P9_DFP_OVERLOAD_2 (BCD_TSTSFI_EQ_DD,	"dtstsfi_eq_dd")
+BU_P9_DFP_OVERLOAD_2 (BCD_TSTSFI_EQ_TD,	"dtstsfi_eq_td")
+
+BU_P9_DFP_OVERLOAD_2 (BCD_TSTSFI_GT,	"dtstsfi_gt")
+BU_P9_DFP_OVERLOAD_2 (BCD_TSTSFI_GT_DD,	"dtstsfi_gt_dd")
+BU_P9_DFP_OVERLOAD_2 (BCD_TSTSFI_GT_TD,	"dtstsfi_gt_td")
+
+BU_P9_DFP_OVERLOAD_2 (BCD_TSTSFI_OV,	"dtstsfi_ov")
+BU_P9_DFP_OVERLOAD_2 (BCD_TSTSFI_OV_DD,	"dtstsfi_ov_dd")
+BU_P9_DFP_OVERLOAD_2 (BCD_TSTSFI_OV_TD,	"dtstsfi_ov_td")
+
 /* 1 argument vector functions added in ISA 3.0 (power9).  */
 BU_P9V_AV_1 (VCTZB,		"vctzb",		CONST,  ctzv16qi2)
 BU_P9V_AV_1 (VCTZH,		"vctzh",		CONST,  ctzv8hi2)
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 4fe392fc317..377a2728f86 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -4123,6 +4123,46 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
   { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
 
+  { P9_BUILTIN_DFP_BCD_TSTSFI_LT, MISC_BUILTIN_BCD_TSTSFI_LT_TD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+  { P9_BUILTIN_DFP_BCD_TSTSFI_LT, MISC_BUILTIN_BCD_TSTSFI_LT_DD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
+  { P9_BUILTIN_DFP_BCD_TSTSFI_LT_TD, MISC_BUILTIN_BCD_TSTSFI_LT_TD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+  { P9_BUILTIN_DFP_BCD_TSTSFI_LT_DD, MISC_BUILTIN_BCD_TSTSFI_LT_DD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
+  { P9_BUILTIN_DFP_BCD_TSTSFI_EQ, MISC_BUILTIN_BCD_TSTSFI_EQ_TD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+  { P9_BUILTIN_DFP_BCD_TSTSFI_EQ, MISC_BUILTIN_BCD_TSTSFI_EQ_DD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
+  { P9_BUILTIN_DFP_BCD_TSTSFI_EQ_TD, MISC_BUILTIN_BCD_TSTSFI_EQ_TD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+  { P9_BUILTIN_DFP_BCD_TSTSFI_EQ_DD, MISC_BUILTIN_BCD_TSTSFI_EQ_DD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
+  { P9_BUILTIN_DFP_BCD_TSTSFI_GT, MISC_BUILTIN_BCD_TSTSFI_GT_TD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+  { P9_BUILTIN_DFP_BCD_TSTSFI_GT, MISC_BUILTIN_BCD_TSTSFI_GT_DD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
+  { P9_BUILTIN_DFP_BCD_TSTSFI_GT_TD, MISC_BUILTIN_BCD_TSTSFI_GT_TD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+  { P9_BUILTIN_DFP_BCD_TSTSFI_GT_DD, MISC_BUILTIN_BCD_TSTSFI_GT_DD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
+  { P9_BUILTIN_DFP_BCD_TSTSFI_OV, MISC_BUILTIN_BCD_TSTSFI_OV_TD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+  { P9_BUILTIN_DFP_BCD_TSTSFI_OV, MISC_BUILTIN_BCD_TSTSFI_OV_DD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
+  { P9_BUILTIN_DFP_BCD_TSTSFI_OV_TD, MISC_BUILTIN_BCD_TSTSFI_OV_TD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+  { P9_BUILTIN_DFP_BCD_TSTSFI_OV_DD, MISC_BUILTIN_BCD_TSTSFI_OV_DD,
+    RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,