gcc/testsuite/ChangeLog:

2017-03-20  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	PR target/79963
	* gcc.target/powerpc/vsu/vec-any-eq-10.c: Add scan-assembler
	directive to assure selection of proper bit using rlwinm insn.
	* gcc.target/powerpc/vsu/vec-any-eq-14.c: Likewise.
	* gcc.target/powerpc/vsu/vec-any-eq-7.c: Likewise.
	* gcc.target/powerpc/vsu/vec-any-eq-8.c: Likewise.
	* gcc.target/powerpc/vsu/vec-any-eq-9.c: Likewise.

gcc/ChangeLog:

2017-03-20  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	PR target/79963
	* config/rs6000/altivec.h (vec_all_ne): Under __cplusplus__ and
	__POWER9_VECTOR__ #ifdef control, change template definition to
	use Power9-specific built-in function.
	(vec_any_eq): Likewise.
	* config/rs6000/vector.md (vector_ae_v2di_p): Change the flag used
	to control outcomes from this test.
	(vector_ae_<mode>p): For VEC_F modes, likewise.


git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@246287 138bc75d-0d04-0410-961f-82ee72b054a4

9 files changed, 30 insertions, 4 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1385d92bcdf..77952ffea1c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2017-03-20  Kelvin Nilsen  <kelvin@gcc.gnu.org>
+
+	PR target/79963
+	* config/rs6000/altivec.h (vec_all_ne): Under __cplusplus__ and
+	__POWER9_VECTOR__ #ifdef control, change template definition to
+	use Power9-specific built-in function.
+	(vec_any_eq): Likewise.
+	* config/rs6000/vector.md (vector_ae_v2di_p): Change the flag used
+	to control outcomes from this test.
+	(vector_ae_<mode>p): For VEC_F modes, likewise.
+
 2017-03-20  Ian Lance Taylor  <iant@google.com>
 
 	* config/i386/i386.c (ix86_function_regparm): Save an extra
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index cd4b724bc52..b9de05a72f0 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -521,9 +521,9 @@ __altivec_scalar_pred(vec_all_nez,
 __altivec_scalar_pred(vec_any_eqz,
   __builtin_vec_vcmpnez_p (__CR6_LT_REV, a1, a2))
 __altivec_scalar_pred(vec_all_ne,
-  __builtin_vec_allne_p (a1, a2))
+  __builtin_vec_vcmpne_p (a1, a2))
 __altivec_scalar_pred(vec_any_eq,
-  __builtin_vec_anyeq_p (a1, a2))
+  __builtin_vec_vcmpae_p (a1, a2))
 #endif
 
 __altivec_scalar_pred(vec_any_ne,
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index fefe5db6aae..e6489a861cd 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -790,7 +790,7 @@
 	  (eq:V2DI (match_dup 1)
 		   (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(lt:SI (reg:CC CR6_REGNO)
+	(eq:SI (reg:CC CR6_REGNO)
 	       (const_int 0)))
    (set (match_dup 0)
 	(xor:SI (match_dup 0)
@@ -837,7 +837,7 @@
 	  (eq:VEC_F (match_dup 1)
 		    (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(lt:SI (reg:CC CR6_REGNO)
+	(eq:SI (reg:CC CR6_REGNO)
 	       (const_int 0)))
    (set (match_dup 0)
 	(xor:SI (match_dup 0)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index abfaa5c2955..2b6d7c6286c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2017-03-20  Kelvin Nilsen  <kelvin@gcc.gnu.org>
+
+	PR target/79963
+	* gcc.target/powerpc/vsu/vec-any-eq-10.c: Add scan-assembler
+	directive to assure selection of proper bit using rlwinm insn.
+	* gcc.target/powerpc/vsu/vec-any-eq-14.c: Likewise.
+	* gcc.target/powerpc/vsu/vec-any-eq-7.c: Likewise.
+	* gcc.target/powerpc/vsu/vec-any-eq-8.c: Likewise.
+	* gcc.target/powerpc/vsu/vec-any-eq-9.c: Likewise.
+
 2017-03-20  Marek Polacek  <polacek@redhat.com>
 	    Paolo Carlini  <paolo.carlini@oracle.com>
 
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-10.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-10.c
index 7a3660e25fc..4e6ca9a694a 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-10.c
@@ -16,3 +16,4 @@ test_any_equal (vector unsigned long long *arg1_p,
 }
 
 /* { dg-final { scan-assembler "vcmpequd." } } */
+/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,27,1" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-14.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-14.c
index 658b4dffa83..2f319bcf2ec 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-14.c
@@ -15,3 +15,4 @@ test_any_equal (vector bool long long *arg1_p, vector bool long long *arg2_p)
 }
 
 /* { dg-final { scan-assembler "vcmpequd." } } */
+/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,27,1" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c
index 5cd9e36f3bb..3693aeafede 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c
@@ -15,3 +15,4 @@ test_any_equal (vector float *arg1_p, vector float *arg2_p)
 }
 
 /* { dg-final { scan-assembler "xvcmpeqsp." } } */
+/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,27,1" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-8.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-8.c
index 038753ff069..9443c75024f 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-8.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-8.c
@@ -15,3 +15,4 @@ test_any_equal (vector double *arg1_p, vector double *arg2_p)
 }
 
 /* { dg-final { scan-assembler "xvcmpeqdp." } } */
+/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,27,1" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-9.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-9.c
index e8c058d6f32..8011a925321 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-9.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-9.c
@@ -15,3 +15,4 @@ test_any_equal (vector long long *arg1_p, vector long long *arg2_p)
 }
 
 /* { dg-final { scan-assembler "vcmpequd." } } */
+/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,27,1" } } */