FRV docs

git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@59901 138bc75d-0d04-0410-961f-82ee72b054a4

3 files changed, 338 insertions, 0 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ce7bfd429a2..b6f7228a6d7 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2002-12-06  Bernd Schmidt  <bernds@redhat.com>
+
+	* doc/invoke.texi: Document FRV port options.
+	* doc/md.texi: Document FRV register classes.
+
 2002-12-07  Gerald Pfeifer  <pfeifer@dbai.tuwien.ac.at>
 
 	* doc/install.texi (Configuration): Improve description of cases
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 79579b9175e..37681c3188b 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -678,6 +678,19 @@ in the following sections.
 -mtarget-align -mno-target-align @gol
 -mlongcalls -mno-longcalls}
 
+@emph{FRV Options}
+@gccoptlist{
+-mgpr-32 -mgpr-64 -mfpr-32 -mfpr-64 -mhard-float -msoft-float @gol
+-malloc-cc -mfixed-cc -mdword -mno-dword -mdouble -mno-double @gol
+-mmedia -mno-media -mmuladd -mno-muladd -mlibrary-pic -macc-4 @gol
+-macc-8 -mpack -mno-pack -mno-eflags -mcond-move -mno-cond-move @gol
+-mscc -mno-scc -mcond-exec -mno-cond-exec -mvliw-branch -mno-vliw-branch @gol
+-mmulti-cond-exec -mno-multi-cond-exec -mnested-cond-exec @gol
+-mno-nested-cond-exec -mtomcat-stats @gol
+-mcpu=@var{cpu}}
+
+
+
 @item Code Generation Options
 @xref{Code Gen Options,,Options for Code Generation Conventions}.
 @gccoptlist{
@@ -5214,6 +5227,7 @@ that macro, which enables you to change the defaults.
 * PDP-11 Options::
 * Xstormy16 Options::
 * Xtensa Options::
+* FRV Options::
 @end menu
 
 @node M680x0 Options
@@ -9939,6 +9953,233 @@ These options are defined for Xstormy16:
 Choose startup files and linker script suitable for the simulator.
 @end table
 
+@node FRV Options
+@subsection FRV Options
+@cindex FRV Options
+
+@table @gcctabopt
+@item -mgpr-32
+@opindex mgpr-32
+
+Only use the first 32 general purpose registers.
+
+@item -mgpr-64
+@opindex mgpr-64
+
+Use all 64 general purpose registers.
+
+@item -mfpr-32
+@opindex mfpr-32
+
+Use only the first 32 floating point registers.
+
+@item -mfpr-64
+@opindex mfpr-64
+
+Use all 64 floating point registers
+
+@item -mhard-float
+@opindex mhard-float
+
+Use hardware instructions for floating point operations.
+
+@item -msoft-float
+@opindex msoft-float
+
+Use library routines for floating point operations.
+
+@item -malloc-cc
+@opindex malloc-cc
+
+Dynamically allocate condition code registers.
+
+@item -mfixed-cc
+@opindex mfixed-cc
+
+Do not try to dynamically allocate condition code registers, only
+use @code{icc0} and @code{fcc0}.
+
+@item -mdword
+@opindex mdword
+
+Change ABI to use double word insns.
+
+@item -mno-dword
+@opindex mno-dword
+
+Do not use double word instructions.
+
+@item -mdouble
+@opindex mdouble
+
+Use floating point double instructions.
+
+@item -mno-double
+@opindex mno-double
+
+Do not use floating point double instructions.
+
+@item -mmedia
+@opindex mmedia
+
+Use media instructions.
+
+@item -mno-media
+@opindex mno-media
+
+Do not use media instructions.
+
+@item -mmuladd
+@opindex mmuladd
+
+Use multiply and add/subtract instructions.
+
+@item -mno-muladd
+@opindex mno-muladd
+
+Do not use multiply and add/subtract instructions.
+
+@item -mlibrary-pic
+@opindex mlibrary-pic
+
+Enable PIC support for building libraries
+
+@item -macc-4
+@opindex macc-4
+
+Use only the first four media accumulator registers.
+
+@item -macc-8
+@opindex macc-8
+
+Use all eight media accumulator registers.
+
+@item -mpack
+@opindex mpack
+
+Pack VLIW instructions.
+
+@item -mno-pack
+@opindex mno-pack
+
+Do not pack VLIW instructions.
+
+@item -mno-eflags
+@opindex mno-eflags
+
+Do not mark ABI switches in e_flags.
+
+@item -mcond-move
+@opindex mcond-move
+
+Enable the use of conditional-move instructions (default).
+
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+
+@item -mno-cond-move
+@opindex mno-cond-move
+
+Disable the use of conditional-move instructions.
+
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+
+@item -mscc
+@opindex mscc
+
+Enable the use of conditional set instructions (default).
+
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+
+@item -mno-scc
+@opindex mno-scc
+
+Disable the use of conditional set instructions.
+
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+
+@item -mcond-exec
+@opindex mcond-exec
+
+Enable the use of conditional execution (default).
+
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+
+@item -mno-cond-exec
+@opindex mno-cond-exec
+
+Disable the use of conditional execution.
+
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+
+@item -mvliw-branch
+@opindex mvliw-branch
+
+Run a pass to pack branches into VLIW instructions (default).
+
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+
+@item -mno-vliw-branch
+@opindex mno-vliw-branch
+
+Do not run a pass to pack branches into VLIW instructions.
+
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+
+@item -mmulti-cond-exec
+@opindex mmulti-cond-exec
+
+Enable optimization of @code{&&} and @code{||} in conditional execution
+(default).
+
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+
+@item -mno-multi-cond-exec
+@opindex mno-multi-cond-exec
+
+Disable optimization of @code{&&} and @code{||} in conditional execution.
+
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+
+@item -mnested-cond-exec
+@opindex mnested-cond-exec
+
+Enable nested conditional execution optimizations (default).
+
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+
+@item -mno-nested-cond-exec
+@opindex mno-nested-cond-exec
+
+Disable nested conditional execution optimizations.
+
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+
+@item -mtomcat-stats
+@opindex mtomcat-stats
+
+Cause gas to print out tomcat statistics.
+
+@item -mcpu=@var{cpu}
+@opindex mcpu
+
+Select the processor type for which to generate code.  Possible values are
+@samp{simple}, @samp{tomcat}, @samp{fr500}, @samp{fr400}, @samp{fr300},
+@samp{frv}.
+
+@end table
+
 @node Xtensa Options
 @subsection Xtensa Options
 @cindex Xtensa Options
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index bc187c511b4..81e599d43bf 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -1750,6 +1750,98 @@ Integer constant in the range 1 to 4 for @code{shladd} instruction
 Memory operand except postincrement and postdecrement
 @end table
 
+@item FRV---@file{frv.h}
+@table @code
+@item a
+Register in the class ACC_REGS (@code{acc0} to @code{acc7}).
+
+@item b
+Register in the class EVEN_ACC_REGS (@code{acc0} to @code{acc7}).
+
+@item c
+Register in the class CC_REGS (@code{fcc0} to @code{fcc3} and @code{icc0} to @code{icc3}).
+
+@item d
+Register in the class GPR_REGS (@code{gr0} to @code{gr63}).
+
+@item e
+Register in the class EVEN_REGS (@code{gr0} to @code{gr63}).
+Odd registers are excluded not in the class but through the use of a machine
+mode larger than 4 bytes.
+
+@item f
+Register in the class FPR_REGS (@code{fr0} to @code{fr63}).
+
+@item h
+Register in the class FEVEN_REGS (@code{fr0} to @code{fr63}).
+Odd registers are excluded not in the class but through the use of a machine
+mode larger than 4 bytes.
+
+@item l
+Register in the class LR_REG (the @code{lr} register).
+
+@item q
+Register in the class QUAD_REGS (@code{gr2} to @code{gr63}).
+Register numbers not divisible by 4 are excluded not in the class but through
+the use of a machine mode larger than 8 bytes.
+
+@item t
+Register in the class ICC_REGS@ (@code{icc0} to @code{icc3}).
+
+@item u
+Register in the class FCC_REGS (@code{fcc0} to @code{fcc3}).
+
+@item v
+Register in the class ICR_REGS (@code{cc4} to @code{cc7}).
+
+@item w
+Register in the class FCR_REGS (@code{cc0} to @code{cc3}).
+
+@item x
+Register in the class QUAD_FPR_REGS (@code{fr0} to @code{fr63}).
+Register numbers not divisible by 4 are excluded not in the class but through
+the use of a machine mode larger than 8 bytes.
+
+@item z
+Register in the class SPR_REGS (@code{lcr} and @code{lr}).
+
+@item A
+Register in the class QUAD_ACC_REGS (@code{acc0} to @code{acc7}).
+
+@item B
+Register in the class ACCG_REGS (@code{accg0} to @code{accg7}).
+
+@item C
+Register in the class CR_REGS (@code{cc0} to @code{cc7}).
+
+@item G
+Floating point constant zero
+
+@item I
+6-bit signed integer constant
+
+@item J
+10-bit signed integer constant
+
+@item L
+16-bit signed integer constant
+
+@item M
+16-bit unsigned integer constant
+
+@item N
+12-bit signed integer constant that is negative - i.e. in the
+range of -2048 to -1
+
+@item O
+Constant zero
+
+@item P
+12-bit signed integer constant that is greater than zero - i.e. in the
+range of 1 to 2047.
+
+@end table
+
 @item IP2K---@file{ip2k.h}
 @table @code
 @item a