aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h
blob: 25087210ec294dc71dca262d85a887f3bf36cbe1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
/*
 * Copyright (C) Marvell International Ltd. and its affiliates
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#ifndef _HIGH_SPEED_ENV_SPEC_H
#define _HIGH_SPEED_ENV_SPEC_H

#include "seq_exec.h"

/*
 * For setting or clearing a certain bit (bit is a number between 0 and 31)
 * in the data
 */
#define SET_BIT(data, bit)		((data) | (0x1 << (bit)))
#define CLEAR_BIT(data, bit)		((data) & (~(0x1 << (bit))))

#define MAX_SERDES_LANES		7	/* as in a39x */

/* Serdes revision */
/* Serdes revision 1.2 (for A38x-Z1) */
#define MV_SERDES_REV_1_2		0x0
/* Serdes revision 2.1 (for A39x-Z1, A38x-A0) */
#define MV_SERDES_REV_2_1		0x1
#define MV_SERDES_REV_NA		0xff

#define	SERDES_REGS_LANE_BASE_OFFSET(lane)	(0x800 * (lane))

#define PEX_X4_ENABLE_OFFS						\
	(hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2 ? 18 : 31)

/* Serdes lane types */
enum serdes_type {
	PEX0,
	PEX1,
	PEX2,
	PEX3,
	SATA0,
	SATA1,
	SATA2,
	SATA3,
	SGMII0,
	SGMII1,
	SGMII2,
	QSGMII,
	USB3_HOST0,
	USB3_HOST1,
	USB3_DEVICE,
	SGMII3,
	XAUI,
	RXAUI,
	DEFAULT_SERDES,
	LAST_SERDES_TYPE
};

/* Serdes baud rates */
enum serdes_speed {
	SERDES_SPEED_1_25_GBPS,
	SERDES_SPEED_1_5_GBPS,
	SERDES_SPEED_2_5_GBPS,
	SERDES_SPEED_3_GBPS,
	SERDES_SPEED_3_125_GBPS,
	SERDES_SPEED_5_GBPS,
	SERDES_SPEED_6_GBPS,
	SERDES_SPEED_6_25_GBPS,
	LAST_SERDES_SPEED
};

/* Serdes modes */
enum serdes_mode {
	PEX_ROOT_COMPLEX_X1,
	PEX_ROOT_COMPLEX_X4,
	PEX_END_POINT_X1,
	PEX_END_POINT_X4,

	SERDES_DEFAULT_MODE, /* not pex */

	SERDES_LAST_MODE
};

struct serdes_map {
	enum serdes_type	serdes_type;
	enum serdes_speed	serdes_speed;
	enum serdes_mode	serdes_mode;
	int			swap_rx;
	int			swap_tx;
};

/* Serdes ref clock options */
enum ref_clock {
	REF_CLOCK_25MHZ,
	REF_CLOCK_100MHZ,
	REF_CLOCK_40MHZ,
	REF_CLOCK_UNSUPPORTED
};

/* Serdes sequences */
enum serdes_seq {
	SATA_PORT_0_ONLY_POWER_UP_SEQ,
	SATA_PORT_1_ONLY_POWER_UP_SEQ,
	SATA_POWER_UP_SEQ,
	SATA_1_5_SPEED_CONFIG_SEQ,
	SATA_3_SPEED_CONFIG_SEQ,
	SATA_6_SPEED_CONFIG_SEQ,
	SATA_ELECTRICAL_CONFIG_SEQ,
	SATA_TX_CONFIG_SEQ1,
	SATA_PORT_0_ONLY_TX_CONFIG_SEQ,
	SATA_PORT_1_ONLY_TX_CONFIG_SEQ,
	SATA_TX_CONFIG_SEQ2,

	SGMII_POWER_UP_SEQ,
	SGMII_1_25_SPEED_CONFIG_SEQ,
	SGMII_3_125_SPEED_CONFIG_SEQ,
	SGMII_ELECTRICAL_CONFIG_SEQ,
	SGMII_TX_CONFIG_SEQ1,
	SGMII_TX_CONFIG_SEQ2,

	PEX_POWER_UP_SEQ,
	PEX_2_5_SPEED_CONFIG_SEQ,
	PEX_5_SPEED_CONFIG_SEQ,
	PEX_ELECTRICAL_CONFIG_SEQ,
	PEX_TX_CONFIG_SEQ1,
	PEX_TX_CONFIG_SEQ2,
	PEX_TX_CONFIG_SEQ3,
	PEX_BY_4_CONFIG_SEQ,
	PEX_CONFIG_REF_CLOCK_25MHZ_SEQ,
	PEX_CONFIG_REF_CLOCK_100MHZ_SEQ,
	PEX_CONFIG_REF_CLOCK_40MHZ_SEQ,

	USB3_POWER_UP_SEQ,
	USB3_HOST_SPEED_CONFIG_SEQ,
	USB3_DEVICE_SPEED_CONFIG_SEQ,
	USB3_ELECTRICAL_CONFIG_SEQ,
	USB3_TX_CONFIG_SEQ1,
	USB3_TX_CONFIG_SEQ2,
	USB3_TX_CONFIG_SEQ3,
	USB3_DEVICE_CONFIG_SEQ,

	USB2_POWER_UP_SEQ,

	SERDES_POWER_DOWN_SEQ,

	SGMII3_POWER_UP_SEQ,
	SGMII3_1_25_SPEED_CONFIG_SEQ,
	SGMII3_TX_CONFIG_SEQ1,
	SGMII3_TX_CONFIG_SEQ2,

	QSGMII_POWER_UP_SEQ,
	QSGMII_5_SPEED_CONFIG_SEQ,
	QSGMII_ELECTRICAL_CONFIG_SEQ,
	QSGMII_TX_CONFIG_SEQ1,
	QSGMII_TX_CONFIG_SEQ2,

	XAUI_POWER_UP_SEQ,
	XAUI_3_125_SPEED_CONFIG_SEQ,
	XAUI_ELECTRICAL_CONFIG_SEQ,
	XAUI_TX_CONFIG_SEQ1,
	XAUI_TX_CONFIG_SEQ2,

	RXAUI_POWER_UP_SEQ,
	RXAUI_6_25_SPEED_CONFIG_SEQ,
	RXAUI_ELECTRICAL_CONFIG_SEQ,
	RXAUI_TX_CONFIG_SEQ1,
	RXAUI_TX_CONFIG_SEQ2,

	SERDES_LAST_SEQ
};

/* The different sequence types for PEX and USB3 */
enum {
	PEX,
	USB3,
	LAST_PEX_USB_SEQ_TYPE
};

enum {
	PEXSERDES_SPEED_2_5_GBPS,
	PEXSERDES_SPEED_5_GBPS,
	USB3SERDES_SPEED_5_GBPS_HOST,
	USB3SERDES_SPEED_5_GBPS_DEVICE,
	LAST_PEX_USB_SPEED_SEQ_TYPE
};

/* The different sequence types for SATA and SGMII */
enum {
	SATA,
	SGMII,
	SGMII_3_125,
	LAST_SATA_SGMII_SEQ_TYPE
};

enum {
	QSGMII_SEQ_IDX,
	LAST_QSGMII_SEQ_TYPE
};

enum {
	XAUI_SEQ_IDX,
	RXAUI_SEQ_IDX,
	LAST_XAUI_RXAUI_SEQ_TYPE
};

enum {
	SATASERDES_SPEED_1_5_GBPS,
	SATASERDES_SPEED_3_GBPS,
	SATASERDES_SPEED_6_GBPS,
	SGMIISERDES_SPEED_1_25_GBPS,
	SGMIISERDES_SPEED_3_125_GBPS,
	LAST_SATA_SGMII_SPEED_SEQ_TYPE
};

extern u8 selectors_serdes_rev1_map[LAST_SERDES_TYPE][MAX_SERDES_LANES];
extern u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES];

u8 hws_ctrl_serdes_rev_get(void);
int mv_update_serdes_select_phy_mode_seq(void);
int hws_board_topology_load(struct serdes_map *serdes_map_array);
enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type,
						   enum serdes_speed baud_rate);
int hws_serdes_seq_init(void);
int hws_serdes_seq_db_init(void);
int hws_power_up_serdes_lanes(struct serdes_map *serdes_config_map);
int hws_ctrl_high_speed_serdes_phy_config(void);
int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up,
			 enum serdes_type serdes_type,
			 enum serdes_speed baud_rate,
			 enum serdes_mode serdes_mode,
			 enum ref_clock ref_clock);
int serdes_power_up_ctrl_ext(u32 serdes_num, int serdes_power_up,
			     enum serdes_type serdes_type,
			     enum serdes_speed baud_rate,
			     enum serdes_mode serdes_mode,
			     enum ref_clock ref_clock);
u32 hws_serdes_silicon_ref_clock_get(void);
int hws_serdes_pex_ref_clock_get(enum serdes_type serdes_type,
				 enum ref_clock *ref_clock);
int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type,
		      enum ref_clock ref_clock);
int hws_update_serdes_phy_selectors(struct serdes_map *serdes_config_map);
u32 hws_serdes_get_phy_selector_val(int serdes_num,
				    enum serdes_type serdes_type);
u32 hws_serdes_get_ref_clock_val(enum serdes_type serdes_type);
u32 hws_serdes_get_max_lane(void);
int hws_get_ext_base_addr(u32 serdes_num, u32 base_addr, u32 unit_base_offset,
			  u32 *unit_base_reg, u32 *unit_offset);
int hws_pex_tx_config_seq(struct serdes_map *serdes_map);
u32 hws_get_physical_serdes_num(u32 serdes_num);
int hws_is_serdes_active(u8 lane_num);

#endif /* _HIGH_SPEED_ENV_SPEC_H */