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author | Tom Rini <trini@konsulko.com> | 2015-07-23 09:02:28 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2015-07-23 09:02:28 -0400 |
commit | 3c9cc70d7153da442575112d9a2643eecd17d534 (patch) | |
tree | b7f2abf20d86dfcb99e4a5406c3dd1b85c176b9f /arch/arm/mach-mvebu/cpu.c | |
parent | 6b9f9eadffb5f64801746593784e12f07f2fadd0 (diff) | |
parent | 9e30b31d20f0b793465d07f056b3d9885f578c0d (diff) |
Merge git://git.denx.de/u-boot-marvell
Diffstat (limited to 'arch/arm/mach-mvebu/cpu.c')
-rw-r--r-- | arch/arm/mach-mvebu/cpu.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 9bc9f002d8..9496d5fc5b 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -163,6 +163,14 @@ static void update_sdram_window_sizes(void) } } +void mmu_disable(void) +{ + asm volatile( + "mrc p15, 0, r0, c1, c0, 0\n" + "bic r0, #1\n" + "mcr p15, 0, r0, c1, c0, 0\n"); +} + #ifdef CONFIG_ARCH_CPU_INIT static void set_cbar(u32 addr) { @@ -172,6 +180,16 @@ static void set_cbar(u32 addr) int arch_cpu_init(void) { +#ifndef CONFIG_SPL_BUILD + /* + * Only with disabled MMU its possible to switch the base + * register address on Armada 38x. Without this the SDRAM + * located at >= 0x4000.0000 is also not accessible, as its + * still locked to cache. + */ + mmu_disable(); +#endif + /* Linux expects the internal registers to be at 0xf1000000 */ writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); set_cbar(SOC_REGS_PHY_BASE + 0xC000); |