Age | Commit message (Collapse) | Author |
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Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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When Secure Hantro VPU is enabled, allow decoding into non protected memory
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Normally, the wdog1 is used by A53 side, and it should
be stopped when A53 domain enter STOP mode. when system
out of PoR, this watchdog is owned by both M7 & A53 side,
then this watchdog can only enter STOP mode only when
both A53 & M7 enter STOP mode. it is not reasonable as
this watchdog is only used by A53 side, so assign wdog1
to domain0(a53 side) only.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit 25ead41a194b87ff9d30e7c4a5c05875a33c432d)
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NXP secure boot flow uses ROM & SPL to load BL3x instead of
TF(Trust Frimware's BL1/BL2) therefore boot chain relies on
BL31's initialization procedure enabled by RESET_TO_BL31 flag.
It might seem not aligned with its documentation about reset
framework however it can be undertstood as BL31's init procedure
still need to enabled even if BL31 doesn't act as reset handler.
In above case, since RESET_TO_BL31 doesn't mean BL31 is reset
handler, it should allow pre-bl31 bootloader to pass config
data into itself. Refer to below mainline patch
https://github.com/ARM-software/arm-trusted-firmware/commit/
25844ff728e4a0e5430ba2032457aba7b780a701
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* origin/ls_v2.6:
LF-4653:- 4 keys secureboot failure resolved
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Changed the size of OCRAM reserved by ROM code and increased the size of CSF
header.
Earlier, 4 keys image was exceeding boundaries and landing in OCRAM location
reserved for ROM usage.
Signed-off by:- Kshitiz Varshney <kshitiz.varshney@nxp.com>
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* origin/imx_v2.6:
LF-6217 fix(imx8ulp): skip the pmic config in dualboot mode
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In dualboot mode, the LPAV is owned by RTD side. When APD enters
low power mode, APD side should not config those PMIC regulators
that used by the resource owned by RTD side.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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* origin/imx_v2.6:
LF-5610 imx8ulp: Allow M33 to access IOMUXC1
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M33 EPDC demo needs to access the IOMUXC1 on Pbridge4 which is
protected by XRDC. Update the configuration to allow the access.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 3ebf7456fa3e24c7a0b361f4819958bc40fdd837)
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* origin/ls_v2.6:
LF-5468: plat: nxp: add DTB overlay feature
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This patch adds DTB address to be passed to both
BL32 and BL33.
BL32 will create the DTB overlay at that address.
BL33 will combine the DTB overlay and DTB passed to it
and boot the kernel.
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
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On i.MX8ULP, the wdog has very strict timing requirement, to make sure
the wdog reset can work well, slow down the APD NIC's frequency before
accessing any wdog's hw registers.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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* origin/imx_v2.6:
LF-5954 fix(plat/imx8ulp): Slow down apd nic frequency when doing wdog reset
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* origin/imx_v2.6: (25 commits)
MA-20199-3 imx8ulp: enable FF-A memory share
MA-20199-2 imx8q: enable FF-A memory share
MA-20199-1 imx8m: enable FF-A memory share
MA-20198 Make separate xlat table and stack address configurable
spd: trusty: Put trusty_shmem_objs_data in its own section
...
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Add FF-A memory share related configs for imx8ulp.
Change-Id: I852b5737345183f86b48bbdbffeb8619bd51a0a1
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Add FF-A memory share related configs for imx8q platforms.
Change-Id: Idd1dcfb9fbc3b57ed48f676eee173285dc9cf830
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Trusty spd implements the memory share subset of FF-A, this
commit enables related configs. As the space to contain TF-A
is limited on some platforms, this commit refines the TF-A size
by:
1. Reduce the TRUSTY_SHARED_MEMORY_OBJ_SIZE from 512KB to
12KB, widevine playback stress pass on imx8mp.
2. Move the xlat table to ocram for imx8mp, imx8mn, imx8mm.
3. Disable FF-A for imx8mq as no more ocram can be used.
Change-Id: I86be12baf96dfbe5ae80c09d672941b233423cad
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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On some ocram limited platforms, the xlat table and stack are
moved to separate address to avoid build break. This commit makes
the address configurable (instead of 0x180000) so it can apply
to other platforms.
Change-Id: I8db72c86d7fa8da9345fb0c132277d1ed8ce9e59
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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If M7 audio enabled, system suspend will changed from DSM to "fast
wakeup" suspend mode, at this phase origal ATF design kept DRAM
,PLLs, clocks same as Linux runtime environment, this will cause even
system is under "fast wakeup" suspend, the power is simlar as run
time. This patch will switch DDR freqs from "normal run time" freq to
400MTS, then make DDR into rentention mode, disable all unused PLLs,
clocks, bypass M7 required clocks to 24M in 'fast wakeup' suspend mode.
Change-Id: Ibc21f250d47475bdb42d9018b9be9ca503387c86
Signed-off-by: Zhipeng Wang <zhipeng.wang_1@nxp.com>
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The imx8mq platform only reserves 64KB (0x910000~0x91ffff)
for ATF usage, which is not enough and will cause build
break like below:
build/imx8mq/release/bl31/bl31.elf section `coherent_ram' will not fit in region `RAM'
BL31 image has exceeded its limit.
region `RAM' overflowed by 4096 bytes
Makefile:846: recipe for target 'build/imx8mq/release/bl31/bl31.elf' failed
make: *** [build/imx8mq/release/bl31/bl31.elf] Error 1
This commit will reduce the code size for imx8mq by doing:
1. Remove ddr4 dvfs support, it's not used on imx8mq.
2. Switch back to xlat_tables v1 instead of xlat_tables v2, which will
occupy more memory. Comment the dynamic mmap in trusty for imx8mq
as it can be removed.
3. Set the 'LOG_LEVEL' as '0' by default so some debug string won't
be built into the final image.
Change-Id: I68f2d6629918a5e7dd616822b5d41ef148f6664b
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Build with trusty will take much more space, which may cause
build break. Reduce the trusty stack size for each cpu to save
some space.
Change-Id: I3bbf21747a4abaef82707a929907575e909ac4d7
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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HAB verify in ATF will touch TCM memory, this commit
adds the memory mapping.
Change-Id: I7511f74420fac769d94db9b1a3cae366bcad6b8e
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Add security configuration(CSU/RDC/TZASC) for android imx8m
platforms.
Change-Id: I76466500f129542a7405ee167251330ed1d770c4
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Add individual config for ddr4 dvfs, it's enabled for imx8m
by default.
Change-Id: Ic4d3b41fd46e7d182b44d76cf38a13e3dc7ad1d4
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Allow non-privileged access to all SNVS registers when no
any TEE is available.
Change-Id: I42906e4ddda0ff484d94323b4ed3c9d28245a5f0
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Update the csu config for imx8m.
Change-Id: Iec3aba43fc765e457fa4f2c4a54a9c18c2565749
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Due to the design issue on A0.1, the HIFI and DSI power domain(PS8,PS14)
need to be on always, so need to keep these power domain on when APD in
active mode. this change need to be reverted when A1 available.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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* origin/imx_v2.6:
LF-5895 fix(plat/imx8ulp) keep hifi & dsi power on in APD active mode
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* origin/ls_v2.6:
fix(layerscape): fix nv_storage assert checking
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* origin/imx_v2.6:
LF-5808-03 plat: imx8ulp: config the pmic in lpm mode
LF-5808-02 plat: imx8ulp: update the upower soc defs
LF-5808-01 plat: imx8ulp: Update the power mode configs
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Add the PMIC config setting used by PD & DPD mode.
when APD enters PD mode, the LDO1(used by DDR) can be shutdown to save power.
when APD enters DPD mode, the BUCK3(supply for APD/LPAV) can be shutdown to save power.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Update the upower soc defs to include the pmic cfg define
used by Low power mode to configure the PMIC regulator/LDOs.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Update the power mode configs to force shutdown all the
necessary power switches to optimize the power consumption.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Fix incorrect assert checking.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ia963bfc053b578f0778ccf06d1dbc2ced4efc266
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* origin/ls_v2.6:
fix(layerscape): fix coverity issue
fix(nxp-ddr): fix coverity issue
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Check return value of mmap_add_dynamic_region().
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I84e257b3052371e18af158c3254f42a1bae0da10
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* origin/imx_v2.6:
LF-5684 plat: imx8ulp: Enable the DDR frequency scaling support
LF-5667 plat: imx8ulp: Update the ddr retention flow
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Enable the DDR frequency scaling support on i.MX8ULP.
Normally, the freq_index define is as below:
0: boot frequency;
1: low frequency(PLL bypassed);
2. high frequency(PLL ON).
Currently, DDR DFS only do frequency switching between Low freq and high freq.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Update the DDR retention flow to include the re-train
sequence after retention.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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