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2022-12-05imx8mq: minor changeslf_2.6lei zhou
2022-11-30imx8mq: enable passing config into bl31 from SPLlei zhou
2022-11-28MMIOT-145: Prevent DCSS to compose outside secure memoryOlivier Masse
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2022-11-28MMIOT-639: CSU regs protected from secure TAlei zhou
2022-11-28MMIOT-675: BL32_BASE set to 0x56000000Olivier Masse
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2022-11-28Add CFG_RDC_SECURE_DATA_PATH flagOlivier Masse
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2022-11-28MMIOT-117: Protect HDCP/HDMI registers when HDCP secure is enabledOlivier Masse
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2022-11-28MMIOT-193 : Setup CSU: VPU access in TZ onlyOlivier Masse
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2022-11-28MMIOT-191: Do not prevent VPU to decode in CMAOlivier Masse
When Secure Hantro VPU is enabled, allow decoding into non protected memory Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2022-11-28MMIOT-152: imx8mq : DRM RDC config addedOlivier Masse
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2022-11-28MLK-24812 plat: imx8mp: Assign wdog1 to domain0 onlyJacky Bai
Normally, the wdog1 is used by A53 side, and it should be stopped when A53 domain enter STOP mode. when system out of PoR, this watchdog is owned by both M7 & A53 side, then this watchdog can only enter STOP mode only when both A53 & M7 enter STOP mode. it is not reasonable as this watchdog is only used by A53 side, so assign wdog1 to domain0(a53 side) only. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com> (cherry picked from commit 25ead41a194b87ff9d30e7c4a5c05875a33c432d)
2022-11-28Use X1(bl31_entrypoint) to receive bl31_configs from SPLlei zhou
2022-11-25imx-atf: allow U-Boot-spl passing config data into BL31lei zhou
NXP secure boot flow uses ROM & SPL to load BL3x instead of TF(Trust Frimware's BL1/BL2) therefore boot chain relies on BL31's initialization procedure enabled by RESET_TO_BL31 flag. It might seem not aligned with its documentation about reset framework however it can be undertstood as BL31's init procedure still need to enabled even if BL31 doesn't act as reset handler. In above case, since RESET_TO_BL31 doesn't mean BL31 is reset handler, it should allow pre-bl31 bootloader to pass config data into itself. Refer to below mainline patch https://github.com/ARM-software/arm-trusted-firmware/commit/ 25844ff728e4a0e5430ba2032457aba7b780a701
2022-10-19imx8mq prototype code to validate the proposallei zhou
2022-05-26LF-6217 fix(imx8ulp): skip the pmic config in dualboot modeJacky Bai
In dualboot mode, the LPAV is owned by RTD side. When APD enters low power mode, APD side should not config those PMIC regulators that used by the resource owned by RTD side. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-05-19LF-5610 imx8ulp: Allow M33 to access IOMUXC1Ye Li
M33 EPDC demo needs to access the IOMUXC1 on Pbridge4 which is protected by XRDC. Update the configuration to allow the access. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit 3ebf7456fa3e24c7a0b361f4819958bc40fdd837)
2022-04-28LF-5954 fix(plat/imx8ulp): Slow down apd nic frequency when doing wdog resetJacky Bai
On i.MX8ULP, the wdog has very strict timing requirement, to make sure the wdog reset can work well, slow down the APD NIC's frequency before accessing any wdog's hw registers. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-04-26MA-20199-3 imx8ulp: enable FF-A memory shareJi Luo
Add FF-A memory share related configs for imx8ulp. Change-Id: I852b5737345183f86b48bbdbffeb8619bd51a0a1 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-20199-2 imx8q: enable FF-A memory shareJi Luo
Add FF-A memory share related configs for imx8q platforms. Change-Id: Idd1dcfb9fbc3b57ed48f676eee173285dc9cf830 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-20199-1 imx8m: enable FF-A memory shareJi Luo
Trusty spd implements the memory share subset of FF-A, this commit enables related configs. As the space to contain TF-A is limited on some platforms, this commit refines the TF-A size by: 1. Reduce the TRUSTY_SHARED_MEMORY_OBJ_SIZE from 512KB to 12KB, widevine playback stress pass on imx8mp. 2. Move the xlat table to ocram for imx8mp, imx8mn, imx8mm. 3. Disable FF-A for imx8mq as no more ocram can be used. Change-Id: I86be12baf96dfbe5ae80c09d672941b233423cad Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-20198 Make separate xlat table and stack address configurableJi Luo
On some ocram limited platforms, the xlat table and stack are moved to separate address to avoid build break. This commit makes the address configurable (instead of 0x180000) so it can apply to other platforms. Change-Id: I8db72c86d7fa8da9345fb0c132277d1ed8ce9e59 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-19640 8MP_powersave:LPA:low power audio feature with PCM512XZhipeng Wang
If M7 audio enabled, system suspend will changed from DSM to "fast wakeup" suspend mode, at this phase origal ATF design kept DRAM ,PLLs, clocks same as Linux runtime environment, this will cause even system is under "fast wakeup" suspend, the power is simlar as run time. This patch will switch DDR freqs from "normal run time" freq to 400MTS, then make DDR into rentention mode, disable all unused PLLs, clocks, bypass M7 required clocks to 24M in 'fast wakeup' suspend mode. Change-Id: Ibc21f250d47475bdb42d9018b9be9ca503387c86 Signed-off-by: Zhipeng Wang <zhipeng.wang_1@nxp.com>
2022-04-26MA-16956 Free space for imx8mq trustyJi Luo
The imx8mq platform only reserves 64KB (0x910000~0x91ffff) for ATF usage, which is not enough and will cause build break like below: build/imx8mq/release/bl31/bl31.elf section `coherent_ram' will not fit in region `RAM' BL31 image has exceeded its limit. region `RAM' overflowed by 4096 bytes Makefile:846: recipe for target 'build/imx8mq/release/bl31/bl31.elf' failed make: *** [build/imx8mq/release/bl31/bl31.elf] Error 1 This commit will reduce the code size for imx8mq by doing: 1. Remove ddr4 dvfs support, it's not used on imx8mq. 2. Switch back to xlat_tables v1 instead of xlat_tables v2, which will occupy more memory. Comment the dynamic mmap in trusty for imx8mq as it can be removed. 3. Set the 'LOG_LEVEL' as '0' by default so some debug string won't be built into the final image. Change-Id: I68f2d6629918a5e7dd616822b5d41ef148f6664b Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-18852 Reduce the trusty stack to save memoryJi Luo
Build with trusty will take much more space, which may cause build break. Reduce the trusty stack size for each cpu to save some space. Change-Id: I3bbf21747a4abaef82707a929907575e909ac4d7 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-19479 imx8mm/imx8mq: Map TCM memory in ATFJi Luo
HAB verify in ATF will touch TCM memory, this commit adds the memory mapping. Change-Id: I7511f74420fac769d94db9b1a3cae366bcad6b8e Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-20186 imx8m: android: add secure configurationJi Luo
Add security configuration(CSU/RDC/TZASC) for android imx8m platforms. Change-Id: I76466500f129542a7405ee167251330ed1d770c4 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-20230 imx8m: Add individual config for ddr4 dvfsJi Luo
Add individual config for ddr4 dvfs, it's enabled for imx8m by default. Change-Id: Ic4d3b41fd46e7d182b44d76cf38a13e3dc7ad1d4 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-20229 imx8m: enable snvs privileged registers accessJi Luo
Allow non-privileged access to all SNVS registers when no any TEE is available. Change-Id: I42906e4ddda0ff484d94323b4ed3c9d28245a5f0 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-20184 imx8m: update csu configJi Luo
Update the csu config for imx8m. Change-Id: Iec3aba43fc765e457fa4f2c4a54a9c18c2565749 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-14LF-5895 fix(plat/imx8ulp) keep hifi & dsi power on in APD active modeJacky Bai
Due to the design issue on A0.1, the HIFI and DSI power domain(PS8,PS14) need to be on always, so need to keep these power domain on when APD in active mode. this change need to be reverted when A1 available. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-04-11LF-5808-03 plat: imx8ulp: config the pmic in lpm modeJacky Bai
Add the PMIC config setting used by PD & DPD mode. when APD enters PD mode, the LDO1(used by DDR) can be shutdown to save power. when APD enters DPD mode, the BUCK3(supply for APD/LPAV) can be shutdown to save power. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-04-11LF-5808-02 plat: imx8ulp: update the upower soc defsJacky Bai
Update the upower soc defs to include the pmic cfg define used by Low power mode to configure the PMIC regulator/LDOs. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-04-11LF-5808-01 plat: imx8ulp: Update the power mode configsJacky Bai
Update the power mode configs to force shutdown all the necessary power switches to optimize the power consumption. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-03-28LF-5684 plat: imx8ulp: Enable the DDR frequency scaling supportJacky Bai
Enable the DDR frequency scaling support on i.MX8ULP. Normally, the freq_index define is as below: 0: boot frequency; 1: low frequency(PLL bypassed); 2. high frequency(PLL ON). Currently, DDR DFS only do frequency switching between Low freq and high freq. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-03-28LF-5667 plat: imx8ulp: Update the ddr retention flowJacky Bai
Update the DDR retention flow to include the re-train sequence after retention. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-03-24LF-5665 plat: imx8ulp: Add gpio podr register save/restoreJacky Bai
Add gpio podr register save/restore. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-03-24LF-4877 plat: imx8ulp: Fix usb unexpected wakeup when system suspendJacky Bai
The 'USBx_PHY_WAKEUP_ISO_DISABLE' bit should be set at least 100us before the 'USBx_PHY_DPD_WAKEUP_EN' to provide the correct USB wakeup functionality, otherwise, the first time system suspend will wakeup wrongly. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com>
2022-03-16MA-20141 imx8m: enable alarm when shutdownJi Luo
Enable SNVS_LPCR_LPTA_EN and SNVS_LPCR_LPWUI_EN during shutdown proces. Change-Id: I566ce759ce7d121a476209836429aeee07cfe49d Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-02-28plat: imx8m: Remove the SDEI support temporarilyJacky Bai
Remove the SDEI suppor temprarily to make sure the DDR DVFS support ok. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2022-02-28LF-5427 plat:imx8 Fix missed SCU wakeup interruptsRanjani Vaidyanathan
Handle corner cases of early of wakeup interrupts. Monitor the status of OS MU interrupt in the IRQSTR as the last step in the suspend process. If an MU interrupt is pending, switch the wakeup source to be irqsteer so that the core can woken up by the SCFW after wfi is executed. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2022-02-28LF-5310 plat: imx8ulp: Update the license for upower apiYe Li
Update the license for upower api to BSD-3-Clause Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2022-02-28LF-5250 imx8ulp: Fix XRDC setting for EPDC displayingYe Li
There are two ports for PXP, one is assigned to DID1 while another is assigned to DID3. The settings for DID1 to DRAM and Pbridge5 are missed which causes EPDC displaying issue. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2022-02-28LF-5161 imx8ulp: Not power off LPAV PD when LPAV owner is RTDYe Li
Upower will check the LPAV ownership when power off the SRAM or PS. if the LPAV owner is not APD, then the power off will return failure. Add simliar checking in SCMI PD driver to skip the power off to avoid failure print causing suspend/resume not work. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-02-28LF-5160 plat: imx8ulp: Update the upower apiJacky Bai
Update the upower API & HAL based on latest upower firmware_048.010.012.008. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-02-28LF-5158 plat: imx8m: Revert "LF-5157 plat: imx8m: Fix the boot hang issue on ↵Jacky Bai
imx8mq/mm/mn" need to get more clear if the mr12/14 update is also apply to 8mq/mm/mn, so revert this patch and keep this feature for 8MP only for now. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2022-02-28LF-5157 plat: imx8m: Fix the boot hang issue on imx8mq/mm/mnJacky Bai
the DDR_IPS size also need to be updated for i.MX8MQ/MM/MN, so fix it. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-02-28LF-5151 plat: imx8m: Backup mr12/14 value from lpddr4 chipJacky Bai
Backup the mr12/14 value as the actual value used is not the one we configured in the ddrc config timing. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-02-28LF-5149 imx8ulp: Fix XRDC for audio SOF caseYe Li
When running audio SOC, HIFI4 DSP (DID2) needs to access SAI5 and eDMA2, and eDMA2 (DID3) will transfer data between SAI5. So update the PDAC configuration for such case, allows SAI5 for DID2 and DID3. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2022-02-28LF-5136 imx8ulp: Protect TEE region for secure access onlyYe Li
Using XRDC MRC4/5/6 to restrict the secure access for TEE DDR memory to protect TEE. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-02-28LF-5118 plat: imx8ulp: Refactor and enable XRDCYe Li
Refactor the XRDC codes to use a static configuration file "xrdc_config.h" for overall XRDC settings. Any change to XRDC setting should modify this file. "xrdc_core.c "is the driver and provide APIs to apply the settings and enable XRDC. All XRDC components are divided into 3 parts according to their power domain dependence: 1. APD (PS6) 2. LPAV (PS16 + DMA2 clock) 3. HIFI (PS8 + DSP clock) Since PS6 and PS16 are default enabled, so we can apply them at boot and resume codes. For HIFI, we follow current codes to apply it when IMX_SIP_HIFI_XRDC is called. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
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