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2022-12-05imx8mq: minor changeslf_2.6lei zhou
2022-11-30imx8mq: enable passing config into bl31 from SPLlei zhou
2022-11-28MMIOT-145: Prevent DCSS to compose outside secure memoryOlivier Masse
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2022-11-28MMIOT-639: CSU regs protected from secure TAlei zhou
2022-11-28MMIOT-675: BL32_BASE set to 0x56000000Olivier Masse
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2022-11-28Add CFG_RDC_SECURE_DATA_PATH flagOlivier Masse
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2022-11-28MMIOT-117: Protect HDCP/HDMI registers when HDCP secure is enabledOlivier Masse
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2022-11-28MMIOT-193 : Setup CSU: VPU access in TZ onlyOlivier Masse
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2022-11-28MMIOT-191: Do not prevent VPU to decode in CMAOlivier Masse
When Secure Hantro VPU is enabled, allow decoding into non protected memory Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2022-11-28MMIOT-152: imx8mq : DRM RDC config addedOlivier Masse
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2022-11-28MLK-24812 plat: imx8mp: Assign wdog1 to domain0 onlyJacky Bai
Normally, the wdog1 is used by A53 side, and it should be stopped when A53 domain enter STOP mode. when system out of PoR, this watchdog is owned by both M7 & A53 side, then this watchdog can only enter STOP mode only when both A53 & M7 enter STOP mode. it is not reasonable as this watchdog is only used by A53 side, so assign wdog1 to domain0(a53 side) only. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com> (cherry picked from commit 25ead41a194b87ff9d30e7c4a5c05875a33c432d)
2022-11-28Use X1(bl31_entrypoint) to receive bl31_configs from SPLlei zhou
2022-11-25imx-atf: allow U-Boot-spl passing config data into BL31lei zhou
NXP secure boot flow uses ROM & SPL to load BL3x instead of TF(Trust Frimware's BL1/BL2) therefore boot chain relies on BL31's initialization procedure enabled by RESET_TO_BL31 flag. It might seem not aligned with its documentation about reset framework however it can be undertstood as BL31's init procedure still need to enabled even if BL31 doesn't act as reset handler. In above case, since RESET_TO_BL31 doesn't mean BL31 is reset handler, it should allow pre-bl31 bootloader to pass config data into itself. Refer to below mainline patch https://github.com/ARM-software/arm-trusted-firmware/commit/ 25844ff728e4a0e5430ba2032457aba7b780a701
2022-10-19imx8mq prototype code to validate the proposallei zhou
2022-04-26MA-20199-1 imx8m: enable FF-A memory shareJi Luo
Trusty spd implements the memory share subset of FF-A, this commit enables related configs. As the space to contain TF-A is limited on some platforms, this commit refines the TF-A size by: 1. Reduce the TRUSTY_SHARED_MEMORY_OBJ_SIZE from 512KB to 12KB, widevine playback stress pass on imx8mp. 2. Move the xlat table to ocram for imx8mp, imx8mn, imx8mm. 3. Disable FF-A for imx8mq as no more ocram can be used. Change-Id: I86be12baf96dfbe5ae80c09d672941b233423cad Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-20198 Make separate xlat table and stack address configurableJi Luo
On some ocram limited platforms, the xlat table and stack are moved to separate address to avoid build break. This commit makes the address configurable (instead of 0x180000) so it can apply to other platforms. Change-Id: I8db72c86d7fa8da9345fb0c132277d1ed8ce9e59 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-19640 8MP_powersave:LPA:low power audio feature with PCM512XZhipeng Wang
If M7 audio enabled, system suspend will changed from DSM to "fast wakeup" suspend mode, at this phase origal ATF design kept DRAM ,PLLs, clocks same as Linux runtime environment, this will cause even system is under "fast wakeup" suspend, the power is simlar as run time. This patch will switch DDR freqs from "normal run time" freq to 400MTS, then make DDR into rentention mode, disable all unused PLLs, clocks, bypass M7 required clocks to 24M in 'fast wakeup' suspend mode. Change-Id: Ibc21f250d47475bdb42d9018b9be9ca503387c86 Signed-off-by: Zhipeng Wang <zhipeng.wang_1@nxp.com>
2022-04-26MA-16956 Free space for imx8mq trustyJi Luo
The imx8mq platform only reserves 64KB (0x910000~0x91ffff) for ATF usage, which is not enough and will cause build break like below: build/imx8mq/release/bl31/bl31.elf section `coherent_ram' will not fit in region `RAM' BL31 image has exceeded its limit. region `RAM' overflowed by 4096 bytes Makefile:846: recipe for target 'build/imx8mq/release/bl31/bl31.elf' failed make: *** [build/imx8mq/release/bl31/bl31.elf] Error 1 This commit will reduce the code size for imx8mq by doing: 1. Remove ddr4 dvfs support, it's not used on imx8mq. 2. Switch back to xlat_tables v1 instead of xlat_tables v2, which will occupy more memory. Comment the dynamic mmap in trusty for imx8mq as it can be removed. 3. Set the 'LOG_LEVEL' as '0' by default so some debug string won't be built into the final image. Change-Id: I68f2d6629918a5e7dd616822b5d41ef148f6664b Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-18852 Reduce the trusty stack to save memoryJi Luo
Build with trusty will take much more space, which may cause build break. Reduce the trusty stack size for each cpu to save some space. Change-Id: I3bbf21747a4abaef82707a929907575e909ac4d7 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-19479 imx8mm/imx8mq: Map TCM memory in ATFJi Luo
HAB verify in ATF will touch TCM memory, this commit adds the memory mapping. Change-Id: I7511f74420fac769d94db9b1a3cae366bcad6b8e Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-20186 imx8m: android: add secure configurationJi Luo
Add security configuration(CSU/RDC/TZASC) for android imx8m platforms. Change-Id: I76466500f129542a7405ee167251330ed1d770c4 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-20230 imx8m: Add individual config for ddr4 dvfsJi Luo
Add individual config for ddr4 dvfs, it's enabled for imx8m by default. Change-Id: Ic4d3b41fd46e7d182b44d76cf38a13e3dc7ad1d4 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-20229 imx8m: enable snvs privileged registers accessJi Luo
Allow non-privileged access to all SNVS registers when no any TEE is available. Change-Id: I42906e4ddda0ff484d94323b4ed3c9d28245a5f0 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-04-26MA-20184 imx8m: update csu configJi Luo
Update the csu config for imx8m. Change-Id: Iec3aba43fc765e457fa4f2c4a54a9c18c2565749 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-03-16MA-20141 imx8m: enable alarm when shutdownJi Luo
Enable SNVS_LPCR_LPTA_EN and SNVS_LPCR_LPWUI_EN during shutdown proces. Change-Id: I566ce759ce7d121a476209836429aeee07cfe49d Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-02-28plat: imx8m: Remove the SDEI support temporarilyJacky Bai
Remove the SDEI suppor temprarily to make sure the DDR DVFS support ok. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2022-02-28LF-5158 plat: imx8m: Revert "LF-5157 plat: imx8m: Fix the boot hang issue on ↵Jacky Bai
imx8mq/mm/mn" need to get more clear if the mr12/14 update is also apply to 8mq/mm/mn, so revert this patch and keep this feature for 8MP only for now. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2022-02-28LF-5157 plat: imx8m: Fix the boot hang issue on imx8mq/mm/mnJacky Bai
the DDR_IPS size also need to be updated for i.MX8MQ/MM/MN, so fix it. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-02-28LF-5151 plat: imx8m: Backup mr12/14 value from lpddr4 chipJacky Bai
Backup the mr12/14 value as the actual value used is not the one we configured in the ddrc config timing. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-02-28LF-4541 plat: imx8m: Fix coverity issue caused by unnecessary header fileJacky Bai
Fix Coverity issue: CID 16300011 caused by unnecessary header file. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-02-28LF-4510-02 plat: imx8m: Fix Coverity issuesJacky Bai
Remove unnecessary header file to fix below Coverity issue CID 16300011 Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-02-28LF-4510-01 plat: imx: fix coverity issueJacky Bai
Fix Coverity issue: CID 6474575: Out-of-bounds access (OVERRUN) CID 11014855: Unused value (UNUSED_VALUE) Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-02-28MA-19048-2 MCU security enhancementJi Luo
Mapping the TCM memory in ATF so HAB verify can pass. Restrict the MCU (Domain 1) write access to RDC and setup the MCU RDC config when MCU starts/stops. Change-Id: I1a90598095171abc9f57d305907b25ce66441cf3 Signed-off-by: Ji Luo <ji.luo@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-02-28MA-19071 imx8mn: workaround for errata ERR050362Ji Luo
Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue. This workaround was done in MCU FW before, move it to TF-A now as MCU should not touch secure world. Change-Id: I2e5bbc764640afeab6ac2f4b202939b59bd3b3f2 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-02-28LF-4197 plat: imx8mp: update the csu csl index on imx8mpJacky Bai
The ocram_a, ocram & ocram_s csu csl index should be 114, 118, 119, so fix it. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-02-28LF-4198 plat: imx8m: Fix the potential array overflowJacky Bai
Check the domain_id to make sure the index passed by the Rich-OS does not exceed the range of the domain arrays. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-02-28MA-19291 imx8mn/imx8mp: Lock ocram secure accessJi Luo
Lock the ocram secure access for imx8mn/imx8mp. Signed-off-by: Ji Luo <ji.luo@nxp.com> Change-Id: Ida3bba565c0f94948b7e04c90075cd3352bbf6e9
2022-02-28LF-4023 plat: imx8mp: Add back the idx define for csu/rdcJacky Bai
Add back the idx define for csu/rdc. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-02-28TEE-639 plat: imx8m: Do not release JR0 to NS if HAB is using itFranck LENORMAND
In case JR0 is used by the HAB for secure boot, it can be used later for authenticating kernel or other binaries. We are checking if the HAB is using the JR by the DID set. Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
2022-02-28MLK-25480 imx8mp: correct idx for csu/rdcPeng Fan
Per i.MX8MP SRM, current idx is wrong, so update them. Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-28MA-18855 plat: imx8mm: Fix BT not work with rpmsg dtsJindong Yue
With rpmsg dts, BT can only work while audio is playing. The reason is that mcu will enter stop mode if no audio task running, this will affect some peripherals, like uart1. Use RDC to set: only domain0(A core) can access uart1. Signed-off-by: Jindong Yue <jindong.yue@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2022-02-28MA-18726 plat: imx8mp: Fix hdmimix handshake hang issueJindong Yue
Enable necessary clocks for HDMIMIX before adb port handshake. Signed-off-by: Jindong Yue <jindong.yue@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2022-02-28MLK-25358 plat: imx8m: Correct the csu sa & hpctrl settingJacky Bai
Correct the csu sa & hpctrl setting. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-02-28MLK-25345 plat: imx8m: Add ddr4 dvfs sw workaround for ERR050712Jacky Bai
APB Write data corruption following MRCTRL0.mr_wr=1 while hardware-driven MR access is occurring When performing a software driven MR access, the following sequence must be done automatically before performing other APB register accesses: 1. Set MRCTRL0.mr_wr=1 2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2) 3. Check for MRSTAT.mr_wr_busy=0 again (for the second time). If not, go to step (2) Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-02-28MLK-25321 plat: imx8m: Add 4000mts frequency config on imx8mJacky Bai
Add the PLL frequency config for 4000mts. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-02-28MLK-24928 plat: imx8mp increase ISP NoC priorityJian Li
Need to increase ISP NoC priority to 0x7 (same as LCDIF panic priority) to avoid overflow in DDR4 EVK board Signed-off-by: Jian Li <jian.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2022-02-28LF-3713 plat: imx8m: Enable the coram_s tz by default on imx8mn/mpJacky Bai
Enable the OCRAM_S TZ for secure protection by default on i.MX8MN/i.MX8MP. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-02-28MLK-25293 iMX8MQ: Add version for B2Ye Li
iMX8MQ B2 chip uses same OCOTP magic value with B1. So read the ROM version to distinguish it with B1. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit dcfce7731ed19c6235f9b1ad3a68fbfe33b69f9a)
2022-02-28MLK-24163 plat: imx8m: Change the ddr4 dvfs debug log levelJacky Bai
This is log is just for debug purpose only. Change the ddr4 dvfs debug log print level to disable this log print by default. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-02-28MLK-24812 plat: imx8mp: Assign wdog1 to domain0 onlyJacky Bai
Normally, the wdog1 is used by A53 side, and it should be stopped when A53 domain enter STOP mode. when system out of PoR, this watchdog is owned by both M7 & A53 side, then this watchdog can only enter STOP mode only when both A53 & M7 enter STOP mode. it is not reasonable as this watchdog is only used by A53 side, so assign wdog1 to domain0(a53 side) only. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
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