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Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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When Secure Hantro VPU is enabled, allow decoding into non protected memory
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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NXP secure boot flow uses ROM & SPL to load BL3x instead of
TF(Trust Frimware's BL1/BL2) therefore boot chain relies on
BL31's initialization procedure enabled by RESET_TO_BL31 flag.
It might seem not aligned with its documentation about reset
framework however it can be undertstood as BL31's init procedure
still need to enabled even if BL31 doesn't act as reset handler.
In above case, since RESET_TO_BL31 doesn't mean BL31 is reset
handler, it should allow pre-bl31 bootloader to pass config
data into itself. Refer to below mainline patch
https://github.com/ARM-software/arm-trusted-firmware/commit/
25844ff728e4a0e5430ba2032457aba7b780a701
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On some ocram limited platforms, the xlat table and stack are
moved to separate address to avoid build break. This commit makes
the address configurable (instead of 0x180000) so it can apply
to other platforms.
Change-Id: I8db72c86d7fa8da9345fb0c132277d1ed8ce9e59
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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The imx8mq platform only reserves 64KB (0x910000~0x91ffff)
for ATF usage, which is not enough and will cause build
break like below:
build/imx8mq/release/bl31/bl31.elf section `coherent_ram' will not fit in region `RAM'
BL31 image has exceeded its limit.
region `RAM' overflowed by 4096 bytes
Makefile:846: recipe for target 'build/imx8mq/release/bl31/bl31.elf' failed
make: *** [build/imx8mq/release/bl31/bl31.elf] Error 1
This commit will reduce the code size for imx8mq by doing:
1. Remove ddr4 dvfs support, it's not used on imx8mq.
2. Switch back to xlat_tables v1 instead of xlat_tables v2, which will
occupy more memory. Comment the dynamic mmap in trusty for imx8mq
as it can be removed.
3. Set the 'LOG_LEVEL' as '0' by default so some debug string won't
be built into the final image.
Change-Id: I68f2d6629918a5e7dd616822b5d41ef148f6664b
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Add security configuration(CSU/RDC/TZASC) for android imx8m
platforms.
Change-Id: I76466500f129542a7405ee167251330ed1d770c4
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Add individual config for ddr4 dvfs, it's enabled for imx8m
by default.
Change-Id: Ic4d3b41fd46e7d182b44d76cf38a13e3dc7ad1d4
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Allow non-privileged access to all SNVS registers when no
any TEE is available.
Change-Id: I42906e4ddda0ff484d94323b4ed3c9d28245a5f0
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Align CSU CSL defines with the rest of the imx8m family
Compile csu and rdc drivers.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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spd trusty requires memory dynamic mapping feature to be
enabled, so we have to use xlat table library v2 instead
of v1.
Test: builds.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Add the SRC SiP handler for M4/M7 boot support on i.MX8M SoC.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the HAB secure boot support for the i.MX8M SoC family.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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This new workaround takes advantage of the per core IMR registers in GPC in
order to unmask the IRQ0, still generated by the 12bit in IOMUX_GPR register
(which now remains always set), so it can only wake up one core at the time.
Also, this entire workaround has now been moved here in TF-A, allowing the
kernel side to be minimal.
Another advantage this workaround brings is the removal of the 50us delay
(which was necessary before in gic_raise_softirq in kernel) by allowing the
core that is waking up to mask his own IRQ0 in the suspend finish callback.
One important change here is the way the cores are woken up in
dram_dvfs_handler. Since the wake up mechanism has changed from asserting the
12th bit in IOMUX_GPR and leaving the IMR1 1st bit on for each core to exactly
the reverse, that is, leaving the IOMUX_GPR 12th bit always set and then
masking/unmasking the IMR1 1st bit for each independent core, we need to use
the imx_gpc_core_wake to wake up the cores.
Also, the 50us udelay is moved to TF-A (inside imx_pwr_domain_off) from kernel
(gic_raise_softirq), since the new cpuidle workaround does not need it in order
to clean the IOMUX_GPC 12bit. For now, the udelay seems to be still needed
in order to delay the affinity info OFF for the dying core. This is something
that needs further investigation.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the dram retention support for i.MX8MQ. As there is
no enough ocram space available before entering TF-A,
so the timing info need to be copied from dram into ocram.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Move the stack & xlat table into ocram_s due to the
ocram is not enough.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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This patch moves all GICv3 driver files into new added
'gicv3.mk' makefile for the benefit of the generic driver
which can evolve in the future without affecting platforms.
The patch adds GICv3 driver configuration flags
'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and
'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in
'GICv3 driver options' section of 'build-option.rst'
document.
NOTE: Platforms with GICv3 driver need to be modified to
include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles.
Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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This patch provides separation of GICD, GICR accessor
functions and adds new macros for GICv3 registers access
as a preparation for GICv3.1 and GICv4 support.
NOTE: Platforms need to modify to include both
'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the
single helper file previously.
Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Add the basic support for opteed SPD on imx8mq & imx8mm.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I6c4855c89dea78d13d172c3d86cf047f829e51ce
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CAAM module must be initialized in secure world
before it can be used in non-secure world.
Change-Id: I042893667ddef99d8b6fc3902847d516d8591996
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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The new API becomes the default one.
Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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AIPSTZ provide access control for all the peripherals connected
to it. In this patch all the perperals are configured accessible
to all the master. it can be customized based the actual use
case.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I5ef5baa1da6906f13a60923d27ede336c61e319a
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The IMX_SIP_BUILDINFO call was implemented for imx8qm and imx8qx but
it's also applicable to imx8m.
This fixes U-Boot not printing commit hash on 8m with upstream TF-A.
Change-Id: Idcfd9729eaaccf329c24e241da325f1f6cd3c880
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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The 'drivers/console/aarch64/console.S' is not needed,
so remove it from build to fix the build error when
'ERROR_DEPRECATED'set.
Change-Id: Id047a355f82fd33298b7e2b49eff289d28eb5b56
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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for the i.MX8M SOCs, part of the code for gpc
and PSCI implementation can be reused and make it
common for all these SoCs. this patch extracts
the common part for reuse.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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NXP's i.MX8MQ uses Cortex-A53 r0p4, enable necessary
erratas for it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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i.MX8MQ is new SOC of NXP's i.MX8M family based on
A53. It can provide industry-leading audio, voice
and video processing for applications that scale
from consumer home audio to industrial building
automation and mobile computers
this patchset add the basic supoort to boot up
the 4 X A53. more feature will be added later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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