imx8mq: enable passing config into bl31 from SPL

2 files changed, 83 insertions, 26 deletions

diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
index ed8886c87..0af591c5d 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
@@ -108,6 +108,14 @@ static void imx8mq_soc_info_init(void)
 	}
 }
 
+static struct bl31_configs {
+        bool       tee_presence;
+        bool       sdp_enable; /* "enable or disable" secure data path */
+        uint32_t   dcss_buf_base, dcss_buf_leng;
+        uint32_t   decode_buf_base, decode_buf_leng;
+        uint32_t   decrypt_buf_base, decrypt_buf_leng;
+} *gp_configs;
+
 #define IMX_DDR_BASE 0x40000000
 
 #ifdef CFG_RDC_SECURE_DATA_PATH
@@ -126,75 +134,116 @@ static void imx8mq_soc_info_init(void)
 
 #if !defined(DECRYPTED_BUFFER_END) || !defined(DECODED_BUFFER_END) || !defined(DCSS_BUFFER_END)
 #define RDC_DISABLED
-#else
-static const struct imx_rdc_cfg rdc_cfg[] = {
+#else /* RDC_ENABLED */
+
+#define RDC_CFG_ITEMS (12-5)
+static struct imx_rdc_cfg g_rdc_cfg[RDC_CFG_ITEMS];
+#if 0
+static const struct imx_rdc_cfg g_rdc_cfg_mda[] = {
 	/* Master domain assignment */
 	RDC_MDAn(RDC_MDA_A53, DID0 | LCK),
 	RDC_MDAn(RDC_MDA_CAAM, DID0 | LCK),
 	RDC_MDAn(RDC_MDA_GPU, DID1 | LCK),
 	RDC_MDAn(RDC_MDA_VPU_DEC, DID2 | LCK),
 	RDC_MDAn(RDC_MDA_DCSS, DID3| LCK),
+	{ 0 }
+};
+#endif
+static void setup_rdc_configs(void)
+{
+	int index = 0;
 
 	/* peripherals domain permission */
-
 	/* memory region */
-
 	/*
 	 * Need to substact offset 0x40000000 from CPU address when
 	 * programming rdc region for i.mx8mq.
 	 */
-
 #ifdef DECRYPTED_BUFFER_START
+	/* Default setting */
+	uint32_t decrypted_buf_start_r = (uint32_t)DECRYPTED_BUFFER_START - IMX_DDR_BASE;
+	uint32_t decrypted_buf_end_r  = (uint32_t)DECRYPTED_BUFFER_END - IMX_DDR_BASE;
+
+	/* if valid config passed in from SPL, override default setting*/
+	if (!gp_configs && gp_configs->decrypt_buf_base > IMX_DDR_BASE) {
+
+		decrypted_buf_start_r = gp_configs->decrypt_buf_base - IMX_DDR_BASE;
+		decrypted_buf_end_r   = gp_configs->decrypt_buf_base +
+		       			gp_configs->decrypt_buf_leng - IMX_DDR_BASE;
+	}
 #ifdef CFG_SECURE_HANTRO_VPU
 	/* Prevent DCSS to compose outside secure buffer */
 	/* Domain 3 no write access to memory region below decrypted video */
-	RDC_MEM_REGIONn(2, 0x0, (uint32_t)DECRYPTED_BUFFER_START - IMX_DDR_BASE, 0xC00000BF),
+	RDC_MEM_REGIONn_INIT(&g_rdc_cfg[index++], 2, 0x0, decrypted_buf_start_r, 0xC00000BF);
 #else
 	/* Prevent VPU to decode outside secure buffer */
 	/* Prevent DCSS to compose outside secure buffer */
 	/* Domain 2+3 no write access to memory region below decrypted video */
-	RDC_MEM_REGIONn(2, 0x0, (uint32_t)DECRYPTED_BUFFER_START - IMX_DDR_BASE, 0xC00000AF),
+	RDC_MEM_REGIONn_INIT(&g_rdc_cfg[index++], 2, 0x0, decrypted_buf_start_r,  0xC00000AF);
 #endif // CFG_SECURE_HANTRO_VPU
 #endif // DECRYPTED_BUFFER_START
 
 #ifdef DECRYPTED_BUFFER_END
 	/* Domain 0 memory region W decrypted video */
 	/* Domain 2 memory region R decrypted video */
-	RDC_MEM_REGIONn(0, (uint32_t)DECRYPTED_BUFFER_START - IMX_DDR_BASE, (uint32_t)DECRYPTED_BUFFER_END - IMX_DDR_BASE, 0xC0000021),
+	RDC_MEM_REGIONn_INIT(&g_rdc_cfg[index++], 0x0, decrypted_buf_start_r, decrypted_buf_end_r, 0xC0000021);
 #endif // DECRYPTED_BUFFER_END
 
 #ifdef DECODED_BUFFER_END
-	/* Domain 2+3 memory region R/W decoded video */
-	RDC_MEM_REGIONn(1, (uint32_t)DECODED_BUFFER_START - IMX_DDR_BASE, (uint32_t)DECODED_BUFFER_END - IMX_DDR_BASE, 0xC00000F0),
+	/* Default setting */
+	uint32_t decode_buf_start_r = (uint32_t)DECODED_BUFFER_START - IMX_DDR_BASE;
+	uint32_t decode_buf_end_r  = (uint32_t)DECODED_BUFFER_END - IMX_DDR_BASE;
+
+	/* if valid config passed in from SPL, override default setting*/
+	if (!gp_configs && gp_configs->decode_buf_base > IMX_DDR_BASE) {
 
+		decode_buf_start_r = gp_configs->decode_buf_base - IMX_DDR_BASE;
+		decode_buf_end_r   = gp_configs->decode_buf_base +
+		       			gp_configs->decode_buf_leng - IMX_DDR_BASE;
+	}
+
+	/* Domain 2+3 memory region R/W decoded video */
+	RDC_MEM_REGIONn_INIT(&g_rdc_cfg[index++], 1, decode_buf_start_r, decode_buf_end_r, 0xC00000F0);
 #ifndef CFG_SECURE_HANTRO_VPU
 	/* Prevent VPU to decode outside secure buffer */
 	/* Domain 2 no write access to memory region above decoded video */
-	RDC_MEM_REGIONn(3, (uint32_t)DECODED_BUFFER_END - IMX_DDR_BASE, 0x100000000 - IMX_DDR_BASE, 0xC00000EF),
+	RDC_MEM_REGIONn_INIT(&g_rdc_cfg[index++], 3, decode_buf_end_r, 0x100000000 - IMX_DDR_BASE, 0xC00000EF);
 #endif // CFG_SECURE_HANTRO_VPU
 
 #endif // DECODED_BUFFER_END
 
 #ifdef DCSS_BUFFER_END
+	/* Default setting */
+	uint32_t dcss_buf_start_r = (uint32_t)DCSS_BUFFER_START - IMX_DDR_BASE;
+	uint32_t dcss_buf_end_r  = (uint32_t)DCSS_BUFFER_END - IMX_DDR_BASE;
+
+	/* if valid config passed in from SPL, override default setting*/
+	if (!gp_configs && gp_configs->dcss_buf_base > IMX_DDR_BASE) {
+
+		dcss_buf_start_r = gp_configs->dcss_buf_base - IMX_DDR_BASE;
+		dcss_buf_end_r   = gp_configs->dcss_buf_base +
+		       			gp_configs->dcss_buf_leng - IMX_DDR_BASE;
+	}
+
 	/* Domain 3 memory region R/W dcss dma region */
-	RDC_MEM_REGIONn(4, (uint32_t)DCSS_BUFFER_START - IMX_DDR_BASE, (uint32_t)DCSS_BUFFER_END - IMX_DDR_BASE, 0xC00000C0),
+	RDC_MEM_REGIONn_INIT(&g_rdc_cfg[index++], 4, dcss_buf_start_r, dcss_buf_end_r, 0xC00000C0);
 
 #ifdef CFG_SECURE_HANTRO_VPU
 	/* Prevent DCSS to compose outside secure buffer */
 	/* Domain 3 no write access to memory region above dcss dma region */
-	RDC_MEM_REGIONn(5, (uint32_t)DCSS_BUFFER_END - IMX_DDR_BASE, 0x100000000 - IMX_DDR_BASE, 0xC00000BF),
+	RDC_MEM_REGIONn_INIT(&g_rdc_cfg[index++], 5, dcss_buf_end_r, 0x100000000 - IMX_DDR_BASE, 0xC00000BF);
 #else
 	/* Prevent VPU to decode outside secure buffer */
 	/* Prevent DCSS to compose outside secure buffer */
 	/* Domain 2+3 no write access to memory region above dcss dma region */
-	RDC_MEM_REGIONn(5, (uint32_t)DCSS_BUFFER_END - IMX_DDR_BASE, 0x100000000 - IMX_DDR_BASE, 0xC00000AF),
+	RDC_MEM_REGIONn_INIT(&g_rdc_cfg[index++], 5, dcss_buf_end_r, 0x100000000 - IMX_DDR_BASE, 0xC00000AF);
 #endif // CFG_SECURE_HANTRO_VPU
 #endif // DCSS_BUFFER_END
 
 	/* Sentinel */
-	{0},
-};
-#endif
+	memset(&g_rdc_cfg[index], 0, sizeof g_rdc_cfg[index]);
+}
+#endif /* RDC_ENABLED */
 
 static const struct imx_csu_cfg csu_cfg_conf[] = {
 	/* peripherals csl setting */
@@ -221,7 +270,11 @@ static void bl31_imx_rdc_setup(void)
 #ifdef RDC_DISABLED
 	ERROR("RDC off \n");
 #else
-	imx_rdc_init(rdc_cfg);
+	setup_rdc_configs();
+#if 0
+	imx_rdc_init(g_rdc_cfg_mda);
+	imx_rdc_init(g_rdc_cfg);
+#endif
 #endif // RDC_DISABLED
 }
 
@@ -259,11 +312,6 @@ static void bl31_tzc380_setup(void)
 				TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
 }
 
-struct bl31_configs {
-        bool       tee_presence;
-        const char *config_1;
-        uint32_t   config_2;
-};
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 			u_register_t arg2, u_register_t arg3)
 {
@@ -308,8 +356,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 	 *  address into BL31.
 	 *  If arg1 is NULL, means no OP-TEE & bl31_configs were detected by SPL.
 	 */
-	struct bl31_configs *configs = (struct bl31_configs *)arg1;
-	bl32_image_ep_info.pc = (!configs->tee_presence)? 0 : BL32_BASE;
+	gp_configs = (struct bl31_configs *)arg1;
+	bl32_image_ep_info.pc = (!gp_configs || !gp_configs->tee_presence)? 0 : BL32_BASE;
 	bl32_image_ep_info.spsr = 0;
 
 	/* Pass TEE base and size to bl33 */
@@ -349,7 +397,6 @@ void bl31_plat_arch_setup(void)
 	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE),
 		MT_MEMORY | MT_RO | MT_SECURE);
 
-	// Map TEE memory
 	mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW);
 
 	mmap_add(imx_mmap);
diff --git a/plat/imx/imx8m/include/imx_rdc.h b/plat/imx/imx8m/include/imx_rdc.h
index 6efa4d1d3..917e147f3 100644
--- a/plat/imx/imx8m/include/imx_rdc.h
+++ b/plat/imx/imx8m/include/imx_rdc.h
@@ -67,6 +67,16 @@ struct imx_rdc_cfg {
 	  .setting.rdc_mem_region[2] = (mrc),	\
 	}
 
+static inline void RDC_MEM_REGIONn_INIT(struct imx_rdc_cfg *item,
+			int index, uint32_t msa, uint32_t mea, uint32_t mrc) {
+
+	item->type = RDC_MEM_REGION;
+	item->index = index;
+	item->setting.rdc_mem_region[0] = msa;
+	item->setting.rdc_mem_region[1] = mea;
+	item->setting.rdc_mem_region[2] = mrc;
+}
+
 void imx_rdc_init(const struct imx_rdc_cfg *cfg);
 
 #endif /* IMX_RDC_H */