diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2016-09-21 11:18:54 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-09-21 15:04:04 +0200 |
| commit | 4baa0ab67d504f3b4318f999631e3f83d0c52c4a (patch) | |
| tree | 25fcdc21f993e7f305d870068cc8fd76b9508f48 /arch/mips/include | |
| parent | b2b135d980a7171c9b0eefbb38861ccbe9a47f97 (diff) | |
MIPS: L2 cache support
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.
If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/cm.h | 38 | ||||
| -rw-r--r-- | arch/mips/include/asm/global_data.h | 3 | ||||
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 5 |
3 files changed, 46 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h index 0261733826..62ecef20fc 100644 --- a/arch/mips/include/asm/cm.h +++ b/arch/mips/include/asm/cm.h @@ -12,8 +12,46 @@ #define GCR_BASE 0x0008 #define GCR_BASE_UPPER 0x000c #define GCR_REV 0x0030 +#define GCR_L2_CONFIG 0x0130 +#define GCR_L2_TAG_ADDR 0x0600 +#define GCR_L2_TAG_ADDR_UPPER 0x0604 +#define GCR_L2_TAG_STATE 0x0608 +#define GCR_L2_TAG_STATE_UPPER 0x060c +#define GCR_L2_DATA 0x0610 +#define GCR_L2_DATA_UPPER 0x0614 /* GCR_REV CM versions */ #define GCR_REV_CM3 0x0800 +/* GCR_L2_CONFIG fields */ +#define GCR_L2_CONFIG_ASSOC_SHIFT 0 +#define GCR_L2_CONFIG_ASSOC_BITS 8 +#define GCR_L2_CONFIG_LINESZ_SHIFT 8 +#define GCR_L2_CONFIG_LINESZ_BITS 4 +#define GCR_L2_CONFIG_SETSZ_SHIFT 12 +#define GCR_L2_CONFIG_SETSZ_BITS 4 +#define GCR_L2_CONFIG_BYPASS (1 << 20) + +#ifndef __ASSEMBLY__ + +#include <asm/io.h> + +static inline void *mips_cm_base(void) +{ + return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE); +} + +static inline unsigned long mips_cm_l2_line_size(void) +{ + unsigned long l2conf, line_sz; + + l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG); + + line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT; + line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0); + return line_sz ? (2 << line_sz) : 0; +} + +#endif /* !__ASSEMBLY__ */ + #endif /* __MIPS_ASM_CM_H__ */ diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index 8533b691b6..0078bbe1b8 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -25,6 +25,9 @@ struct arch_global_data { unsigned short l1i_line_size; unsigned short l1d_line_size; #endif +#ifdef CONFIG_MIPS_L2_CACHE + unsigned short l2_line_size; +#endif }; #include <asm-generic/global_data.h> diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index cd4f952df0..b4c2dff483 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -485,9 +485,13 @@ #define MIPS_CONF1_TLBS_SIZE (6) #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) +#define MIPS_CONF2_SA_SHF 0 #define MIPS_CONF2_SA (_ULCAST_(15) << 0) +#define MIPS_CONF2_SL_SHF 4 #define MIPS_CONF2_SL (_ULCAST_(15) << 4) +#define MIPS_CONF2_SS_SHF 8 #define MIPS_CONF2_SS (_ULCAST_(15) << 8) +#define MIPS_CONF2_L2B (_ULCAST_(1) << 12) #define MIPS_CONF2_SU (_ULCAST_(15) << 12) #define MIPS_CONF2_TA (_ULCAST_(15) << 16) #define MIPS_CONF2_TL (_ULCAST_(15) << 20) @@ -551,6 +555,7 @@ #define MIPS_CONF5_MVH (_ULCAST_(1) << 5) #define MIPS_CONF5_FRE (_ULCAST_(1) << 8) #define MIPS_CONF5_UFE (_ULCAST_(1) << 9) +#define MIPS_CONF5_L2C (_ULCAST_(1) << 10) #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) #define MIPS_CONF5_EVA (_ULCAST_(1) << 28) #define MIPS_CONF5_CV (_ULCAST_(1) << 29) |