diff options
| author | Ye Li <ye.li@nxp.com> | 2020-11-02 19:02:21 -0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2020-11-03 00:47:17 -0800 |
| commit | c189dad00743c7a3fcd80d716498289fa7cb2c40 (patch) | |
| tree | 13e17ba53918ac556b4e2db9348df8ba593a4128 | |
| parent | ea48b544581d630bc031a7968a90b2fcf328424a (diff) | |
MLK-24958-1 clk: imx8qxp/dxl: Add clock support for LCDIF
Add relevant clocks tree for LCDIF. According to design, LCDIF has
a slice and a dedicated eLCDIF PLL for pixel clock.
On iMX8QXP, there is pixel link mux which is muxed with LCDIF IOs.
It uses slice bypass reference clock for pix clock input.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | drivers/clk/imx/clk-imx8qxp.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 8ccb5551a7..995d34cdbc 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -50,6 +50,11 @@ static struct imx8_clks imx8qxp_clks[] = { CLK_4( IMX8QXP_LSIO_FSPI0_DIV, "FSPI0_DIV", SC_R_FSPI_0, SC_PM_CLK_PER ), CLK_4( IMX8QXP_GPMI_BCH_IO_DIV, "GPMI_IO_DIV", SC_R_NAND, SC_PM_CLK_MST_BUS ), CLK_4( IMX8QXP_GPMI_BCH_DIV, "GPMI_BCH_DIV", SC_R_NAND, SC_PM_CLK_PER ), + + CLK_4( IMX8QXP_ELCDIF_PLL_DIV, "ELCDIF_PLL_DIV", SC_R_ELCDIF_PLL, SC_PM_CLK_PLL ), + CLK_4( IMX8QXP_LCD_PXL_DIV, "LCD_PXL_DIV", SC_R_LCD_0, SC_PM_CLK_MISC0 ), + CLK_4( IMX8QXP_LCD_DIV, "LCD_DIV", SC_R_LCD_0, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_LCD_PXL_BYPASS_DIV, "LCD_PXL_BYPASS_DIV", SC_R_LCD_0, SC_PM_CLK_BYPASS ), }; static struct imx8_fixed_clks imx8qxp_fixed_clks[] = { @@ -192,6 +197,7 @@ static struct imx8_lpcg_clks imx8qxp_lpcg_clks[] = { CLK_5( IMX8QXP_HSIO_PHY_X1_APB_CLK, "HSIO_PHY_X1_APB_CLK", 16, HSIO_PHY_X1_LPCG, IMX8QXP_HSIO_PER_CLK ), CLK_5( IMX8QXP_HSIO_GPIO_CLK, "HSIO_GPIO_CLK", 16, HSIO_GPIO_LPCG, IMX8QXP_HSIO_PER_CLK ), CLK_5( IMX8QXP_HSIO_PHY_X1_PCLK, "HSIO_PHY_X1_PCLK", 0, HSIO_PHY_X1_LPCG, 0 ), + CLK_5( IMX8QXP_LCD_IPG_CLK, "LCD_IPG_CLK", 16, LCD_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ), }; struct imx8_mux_clks imx8qxp_mux_clks[] = { @@ -201,6 +207,11 @@ struct imx8_mux_clks imx8qxp_mux_clks[] = { IMX8QXP_CONN_PLL1_CLK, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY ), CLK_MUX( IMX8QXP_SDHC2_SEL, "SDHC2_SEL", IMX8QXP_SDHC2_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CONN_PLL0_CLK, IMX8QXP_CONN_PLL1_CLK, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY ), + + CLK_MUX( IMX8QXP_LCD_PXL_SEL, "LCD_PXL_SEL", IMX8QXP_LCD_PXL_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY, + IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY, IMX8QXP_LCD_PXL_BYPASS_DIV ), + CLK_MUX( IMX8QXP_LCD_SEL, "LCD_SEL", IMX8QXP_LCD_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY, + IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY, IMX8QXP_ELCDIF_PLL_DIV ), }; struct imx8_clks_collect imx8qxp_clk_collect = { |