From 270367fbf7e2d3cb004257a7d1123fc89d58eba6 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Tue, 27 Aug 2019 16:21:10 +0300 Subject: plat: marvell: armada: a3k: allow image load to RAM address 0 Marvell uses RAM address 0x0 for loading BL33 stage images. When ATF is built with DEBUG=1, its IO subsystem fails on assert checking the destination RAM address != 0. This patch adds PLAT_ALLOW_ZERO_ADDR_COPY to A3K platform allowing to bypass the above check in debug mode. Change-Id: I687e35cb2e9dc3166bdaa81b3904c20b784c5c6a Signed-off-by: Konstantin Porotchkin --- plat/marvell/armada/a3k/common/include/platform_def.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'plat/marvell') diff --git a/plat/marvell/armada/a3k/common/include/platform_def.h b/plat/marvell/armada/a3k/common/include/platform_def.h index 61c7dfe70..3d839f820 100644 --- a/plat/marvell/armada/a3k/common/include/platform_def.h +++ b/plat/marvell/armada/a3k/common/include/platform_def.h @@ -70,6 +70,14 @@ * PLAT_MARVELL_FIP_BASE = 0x4120000 */ +/* + * Since BL33 is loaded by BL2 (and validated by BL31) to DRAM offset 0, + * it is allowed to load/copy images to 'NULL' pointers + */ +#if defined(IMAGE_BL2) || defined(IMAGE_BL31) +#define PLAT_ALLOW_ZERO_ADDR_COPY +#endif + #define PLAT_MARVELL_ATF_BASE 0x4000000 #define PLAT_MARVELL_ATF_LOAD_ADDR \ (PLAT_MARVELL_ATF_BASE + 0x100000) -- cgit v1.2.3