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For git repo without tag, the build string does not have tag and
commit with "g" prefix. Update the parser for this case.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
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This is log is just for debug purpose only. Change the
ddr4 dvfs debug log print level to disable this log print
by default.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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This cause RCU stall on i.MX platform, because timer control register
was cleared to 0, and non secure timer interrupt was disabled
during OP-TEE executing tests.
This reverts commit 43f999a7e35db5bdbb5af6dfc7efc46f6ecab443.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Normally, the wdog1 is used by A53 side, and it should
be stopped when A53 domain enter STOP mode. when system
out of PoR, this watchdog is owned by both M7 & A53 side,
then this watchdog can only enter STOP mode only when
both A53 & M7 enter STOP mode. it is not reasonable as
this watchdog is only used by A53 side, so assign wdog1
to domain0(a53 side) only.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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Fix the out of bound access to the rank setting array.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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when the DSP LPA buffer is in OCRAM, dram can be put into retention to save
power. This support is missed when removing the i.MX8MP A0 support, so add
it back.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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It seems the DRAM APB clock root slice can NOT work normally
if the PLLs is power down in DSM mode. So update this clock
slice's setting explictly to make it work. This piece of code
is there for a long while on previous release, so just add
it back to align with previous flow.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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on i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K,
currently, OCRAM @0x960000-0x980000 is reserved for BL31, it will
leave the last 64KB in non-continuous space. To provide a continuous
384KB + 64KB space for generic use, so Move the BL31 space to
0x970000-0x990000 range.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 3d23f9b3458194f6c76f9ba66fb52240f2485d44)
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The VC8000E's clock should be gated before power up it to make
sure the noc port can be synced successfully during vc8000e
reset.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit aa3fee73c322ccc664f9b7715412d929e55c914f)
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The VPU reset & memrepair workaround is only for i.MX8MP
A0 silicon. As the A0 will not be supported anymore, so
drop these workaround
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
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DD3L EVK board only has 512MB of DDR.
move OP-TEE mapping for all the 8MN boards.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
(cherry picked from commit 5d80923c8c440ebf4449adf44c05932c35a24a9b)
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Use sc_rm_memreg_frag() instead of sc_rm_memreg_alloc() to avoid memory partition
overlay, sc_rm_memreg_frag() will return non-overlapping regions.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Add DRAM PLL frequency setting for 3200mts.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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This reverts commit 8567103ef94b1abb52f9fb053bd6118913878d74.
As the SDEI support has conflict with the busfreq EL3 interrupt
handling, so just revert it for now.
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Only enable the power domains that need to be boot on by default.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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move the gpc reg offset, bit define & macro to a separate header
file for code reuse.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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The dfimisc reg value should be shift right 8 bit to
get the current fsp.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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if LPA buffer is in OCRAM, then the LPA flag is 0xD,
if LPA buffer is in DRAM, then the LPA flag is 0x1D.
when audio buffer is in DRAM, then DRAM can be put into
retention when A53 is suspended.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Tested-by: Bing Song <bing.song@nxp.com>
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re-enable csu and rdc test for use of the test team
only enable if CSU_RDC_TEST is defined.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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Align CSU CSL defines with the rest of the imx8m family
Compile csu and rdc drivers.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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update umctl2's setting based on phy training CDD value
to workaround the rank-to-rank space issue.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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the dfiphymaster setting need to be save/restore to make sure
it aligned with the initial config.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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the DDR3L & DDR4 can share same piece of code of DVFS, so update
the ddr4 dvfs to support DDR3L too.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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the bitfield of active_ranks in MSTR is defined as below.
Correct the rank num get in dram_info.
0x01: one rank;
0x11: two rank;
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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The anamix PLL override setting should be cleared after system resume.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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Keep the audiomix power domain always on if the LPA is active &
doing audio playback.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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When system entering DSM mode, the main NOC wrapper only need to
be on if any of the MIX with ADB400 port is on, so update the flow
for this.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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On i.Mx8MQ, the actual system counter freq is 8333333Hz,
have some trailing part, so get the actual freq from the system
counter module register.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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Fix assignment error in CSU_SA() and CSU_HPCTRL().
Change-Id: Ia7210745c4e91e33a1ea825ef2678b2d912a066d
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
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In step12, remove the while loop waiting to align
with the ddr4 dvfs flow on imx_2.0.y.
Tested-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Fix build break for iMX8MQ.
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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On i.MX8MP, the SRC GPR9(0x94) is used by memory repair, so choose
SRC GPR10(0x98) as the LPA status sync register. Add use '==' instead
of '&' for LPA active statue check.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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Support stop M7 with SIP call.
Per IC team, to rekick M7 need follow steps.
If M7 already in WFI, perform below steps.
a) Set [0x303A_002C].0=0 [ request SLEEPHOLDREQn ]
b) Wait [0x303A_00EC].1 = 0 [ wait SLEEPHOLDACKn ]
c) Set GPR.CPUWAIT=1
d) Set [0x303A_002C].0=1 [ de-assert SLEEPHOLDREQn ]
e) Set SRC_M7_RCR[3:0] = 0xE0 [ reset M7 core/plat ]
f) Wait SRC_M7_RCR[3:0] = 0x8
g) Init TCM or DDR
h) Set GPR.INITVTOR
i) Set GPR.CPUWAIT=0, M7 starting running
Add a timeout check, if timeout, still perform force reset, in this
way no need to rely on M7 team's image wfi support ready.
Return a1,a2 to caller to check timeout or reset fail.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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This part of code is still needed by uboot, so add
it back.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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On i.MX8MN & i.MX8MP, the M core enabled check should
relay on the IOMUX GPR CPU_WAIT bit, when this bit is
cleared, it means M core is active & running, so refine
the m4 enabled check method.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Allow OP-TEE to generate a device-tree overlay binary
that will be applied by u-boot on the regular dtb.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Updating the CPU CORE power up timing to make sure
the RDC reload is done before CPU start to run code
in OCRAM space.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Current reset uses WDOG timeout function and default timeout
value is set to 0.5 second. However, it is better to trigger
reset immediately to speed up reboot process as well as prevent
the scenario of WDOG_B toggling later than CPU reset and PMIC
does NOT reset.
Set the WDE bit when IMX_WDOG_B_RESET is not enabled, or
reboot will fail.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Align code style between 8mq, 8mm and 8mn files.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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Add trusty support for imx8mq, default load address
and size for trusty os will be 0xfe000000 and 0x2000000.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry picked from a708794ccde53d8253a74ff578ca9d5258971690)
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Add trusty support for imx8mn, default load address and
size of trusty are 0xbe000000 and 0x2000000.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry picked from commit 1566947ab431388906d71a1fb48e802fc9a1eec9)
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Add trusty support for imx8mm, default load address
and size of trusty are 0xbe000000 anx 0x2000000.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 28d3f0fa26ff11efb98281ed603b6f44cea3c6c5)
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spd trusty requires memory dynamic mapping feature to be
enabled, so we have to use xlat table library v2 instead
of v1.
Test: builds.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Replace the magic number index with enum type to make RDC/CSU config
more clear for user.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the M core low power audio support on i.MX8M.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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