diff options
| -rw-r--r-- | bl1/bl1_main.c | 29 | ||||
| -rw-r--r-- | include/lib/aarch64/arch.h | 19 | ||||
| -rw-r--r-- | include/lib/aarch64/arch_helpers.h | 4 | ||||
| -rw-r--r-- | plat/fvp/bl2_fvp_setup.c | 2 | ||||
| -rw-r--r-- | plat/fvp/include/platform_def.h | 1 | ||||
| -rw-r--r-- | plat/juno/bl2_plat_setup.c | 2 | ||||
| -rw-r--r-- | plat/juno/include/platform_def.h | 1 |
7 files changed, 45 insertions, 13 deletions
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index 491fd5cfc..a5db08557 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -114,21 +114,36 @@ void bl1_main(void) INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT); -#if DEBUG - unsigned long sctlr_el3 = read_sctlr_el3(); -#endif image_info_t bl2_image_info = { {0} }; entry_point_info_t bl2_ep = { {0} }; meminfo_t *bl1_tzram_layout; meminfo_t *bl2_tzram_layout = 0x0; int err; +#if DEBUG + unsigned long val; /* * Ensure that MMU/Caches and coherency are turned on */ - assert(sctlr_el3 | SCTLR_M_BIT); - assert(sctlr_el3 | SCTLR_C_BIT); - assert(sctlr_el3 | SCTLR_I_BIT); + val = read_sctlr_el3(); + assert(val | SCTLR_M_BIT); + assert(val | SCTLR_C_BIT); + assert(val | SCTLR_I_BIT); + /* + * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the + * provided platform value + */ + val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; + /* + * If CWG is zero, then no CWG information is available but we can + * at least check the platform value is less than the architectural + * maximum. + */ + if (val != 0) + assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); + else + assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); +#endif /* Perform remaining generic architectural setup from EL3 */ bl1_arch_setup(); diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 5e2167374..912643d26 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -302,6 +302,23 @@ ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) +/* + * CTR_EL0 definitions + */ +#define CTR_CWG_SHIFT 24 +#define CTR_CWG_MASK 0xf +#define CTR_ERG_SHIFT 20 +#define CTR_ERG_MASK 0xf +#define CTR_DMINLINE_SHIFT 16 +#define CTR_DMINLINE_MASK 0xf +#define CTR_L1IP_SHIFT 14 +#define CTR_L1IP_MASK 0x3 +#define CTR_IMINLINE_SHIFT 0 +#define CTR_IMINLINE_MASK 0xf + +#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */ +#define SIZE_FROM_LOG2_WORDS(n) (4 << (n)) + /* Physical timer control register bit fields shifts and masks */ #define CNTP_CTL_ENABLE_SHIFT 0 diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index ceb88e477..b7ab3da69 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -281,6 +281,8 @@ DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) DEFINE_SYSREG_READ_FUNC(isr_el1) +DEFINE_SYSREG_READ_FUNC(ctr_el0) + /* GICv3 System Registers */ DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) diff --git a/plat/fvp/bl2_fvp_setup.c b/plat/fvp/bl2_fvp_setup.c index 364833fe9..23c8593d7 100644 --- a/plat/fvp/bl2_fvp_setup.c +++ b/plat/fvp/bl2_fvp_setup.c @@ -73,7 +73,7 @@ extern unsigned long __COHERENT_RAM_END__; /* Data structure which holds the extents of the trusted SRAM for BL2 */ static meminfo_t bl2_tzram_layout -__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE))); +__attribute__ ((aligned(CACHE_WRITEBACK_GRANULE))); /* Assert that BL3-1 parameters fit in shared memory */ CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t)) < diff --git a/plat/fvp/include/platform_def.h b/plat/fvp/include/platform_def.h index 6713c5c28..59b242d4b 100644 --- a/plat/fvp/include/platform_def.h +++ b/plat/fvp/include/platform_def.h @@ -96,7 +96,6 @@ # define BL33_CERT_NAME "bl33.crt" #endif /* TRUSTED_BOARD_BOOT */ -#define PLATFORM_CACHE_LINE_SIZE 64 #define PLATFORM_CLUSTER_COUNT 2ull #define PLATFORM_CLUSTER0_CORE_COUNT 4 #define PLATFORM_CLUSTER1_CORE_COUNT 4 diff --git a/plat/juno/bl2_plat_setup.c b/plat/juno/bl2_plat_setup.c index 8e7b2a0ae..d7b2f7637 100644 --- a/plat/juno/bl2_plat_setup.c +++ b/plat/juno/bl2_plat_setup.c @@ -75,7 +75,7 @@ extern unsigned long __COHERENT_RAM_END__; /* Data structure which holds the extents of the trusted RAM for BL2 */ static meminfo_t bl2_tzram_layout -__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE))); +__attribute__ ((aligned(CACHE_WRITEBACK_GRANULE))); /******************************************************************************* * Structure which holds the arguments which need to be passed to BL3-1 diff --git a/plat/juno/include/platform_def.h b/plat/juno/include/platform_def.h index 9eb305358..5c220698c 100644 --- a/plat/juno/include/platform_def.h +++ b/plat/juno/include/platform_def.h @@ -87,7 +87,6 @@ # define BL33_CERT_NAME "bl33.crt" #endif /* TRUSTED_BOARD_BOOT */ -#define PLATFORM_CACHE_LINE_SIZE 64 #define PLATFORM_CLUSTER_COUNT 2 #define PLATFORM_CORE_COUNT 6 #define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \ |