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authorNorbert Werner <opensource@lab-w.org>2020-01-19 14:51:01 +0100
committerOlivier Deprez <olivier.deprez@arm.com>2020-01-22 10:36:23 +0000
commit67878cb0e5e6bb7fa62499491dc4f0adc6a6a3f7 (patch)
treeb53d006be4e12d9b97f922e567cb733919f377b9 /plat/xilinx
parentc9c0b66f9ae4b31431c661bd07c1a835d1ebf02a (diff)
Xilinx zynqmp: add missing pin control group for ethernet 0.
Signed-off-by: Norbert Werner <opensource@lab-w.org> Change-Id: I3264515e5901689328861964ff664ff08b6e852c
Diffstat (limited to 'plat/xilinx')
-rw-r--r--plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
index a900057e8..4b8dfb614 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -1477,6 +1477,7 @@ static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = {
},
[PINCTRL_PIN_26] = {
.groups = &((uint16_t []) {
+ PINCTRL_GRP_ETHERNET0_0,
PINCTRL_GRP_GEMTSU0_0,
PINCTRL_GRP_NAND0_1_CE,
PINCTRL_GRP_PMU0_0,