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| author | Manish Pandey <manish.pandey2@arm.com> | 2020-01-24 10:02:07 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2020-01-24 10:02:07 +0000 |
| commit | 4e1b0b193cad14ad2d67819ab34b3fa58f2e5c04 (patch) | |
| tree | 5562a029b88256691f4f28e385b000838f566a7d /plat/xilinx | |
| parent | b25340793e0920db6e5d1ce8e7852ba872ccfa95 (diff) | |
| parent | 67878cb0e5e6bb7fa62499491dc4f0adc6a6a3f7 (diff) | |
Merge "Xilinx zynqmp: add missing pin control group for ethernet 0." into integration
Diffstat (limited to 'plat/xilinx')
| -rw-r--r-- | plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c index a900057e8..4b8dfb614 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -1477,6 +1477,7 @@ static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = { }, [PINCTRL_PIN_26] = { .groups = &((uint16_t []) { + PINCTRL_GRP_ETHERNET0_0, PINCTRL_GRP_GEMTSU0_0, PINCTRL_GRP_NAND0_1_CE, PINCTRL_GRP_PMU0_0, |