rpi: move plat_helpers.S to common

The plat_helpers.S file was almost identical between its RPi3 and RPi4
versions. Unify the two files, moving it into the common/ directory.

This adds a plat_rpi_get_model() function, which can be used to trigger
RPi4 specific action, detected at runtime. We use that to do the RPi4
specific L2 cache initialisation.

Change-Id: I2295704fd6dde7c76fe83b6d98c7bf998d4bf074
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

3 files changed, 2 insertions, 187 deletions

diff --git a/plat/rpi/rpi4/aarch64/plat_helpers.S b/plat/rpi/rpi4/aarch64/plat_helpers.S
deleted file mode 100644
index fac1b2075..000000000
--- a/plat/rpi/rpi4/aarch64/plat_helpers.S
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <assert_macros.S>
-#include <platform_def.h>
-#include <cortex_a72.h>
-
-	.globl	plat_crash_console_flush
-	.globl	plat_crash_console_init
-	.globl	plat_crash_console_putc
-	.globl	platform_mem_init
-	.globl	plat_get_my_entrypoint
-	.globl	plat_is_my_cpu_primary
-	.globl	plat_my_core_pos
-	.globl	plat_reset_handler
-	.globl	plat_rpi3_calc_core_pos
-	.globl	plat_secondary_cold_boot_setup
-
-	/* -----------------------------------------------------
-	 *  unsigned int plat_my_core_pos(void)
-	 *
-	 *  This function uses the plat_rpi3_calc_core_pos()
-	 *  definition to get the index of the calling CPU.
-	 * -----------------------------------------------------
-	 */
-func plat_my_core_pos
-	mrs	x0, mpidr_el1
-	b	plat_rpi3_calc_core_pos
-endfunc plat_my_core_pos
-
-	/* -----------------------------------------------------
-	 *  unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr);
-	 *
-	 *  CorePos = (ClusterId * 4) + CoreId
-	 * -----------------------------------------------------
-	 */
-func plat_rpi3_calc_core_pos
-	and	x1, x0, #MPIDR_CPU_MASK
-	and	x0, x0, #MPIDR_CLUSTER_MASK
-	add	x0, x1, x0, LSR #6
-	ret
-endfunc plat_rpi3_calc_core_pos
-
-	/* -----------------------------------------------------
-	 * unsigned int plat_is_my_cpu_primary (void);
-	 *
-	 * Find out whether the current cpu is the primary
-	 * cpu.
-	 * -----------------------------------------------------
-	 */
-func plat_is_my_cpu_primary
-	mrs	x0, mpidr_el1
-	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
-	cmp	x0, #RPI4_PRIMARY_CPU
-	cset	w0, eq
-	ret
-endfunc plat_is_my_cpu_primary
-
-	/* -----------------------------------------------------
-	 * void plat_secondary_cold_boot_setup (void);
-	 *
-	 * This function performs any platform specific actions
-	 * needed for a secondary cpu after a cold reset e.g
-	 * mark the cpu's presence, mechanism to place it in a
-	 * holding pen etc.
-	 * -----------------------------------------------------
-	 */
-func plat_secondary_cold_boot_setup
-	/* Calculate address of our hold entry */
-	bl	plat_my_core_pos
-	lsl	x0, x0, #3
-	mov_imm	x2, PLAT_RPI3_TM_HOLD_BASE
-	add	x0, x0, x2
-
-	/*
-	 * This code runs way before requesting the warmboot of this core,
-	 * so it is possible to clear the mailbox before getting a request
-	 * to boot.
-	 */
-	mov	x1, PLAT_RPI3_TM_HOLD_STATE_WAIT
-	str	x1,[x0]
-
-	/* Wait until we have a go */
-poll_mailbox:
-	wfe
-	ldr	x1, [x0]
-	cmp	x1, PLAT_RPI3_TM_HOLD_STATE_GO
-	bne	poll_mailbox
-
-	/* Jump to the provided entrypoint */
-	mov_imm	x0, PLAT_RPI3_TM_ENTRYPOINT
-	ldr	x1, [x0]
-	br	x1
-endfunc plat_secondary_cold_boot_setup
-
-	/* ---------------------------------------------------------------------
-	 * uintptr_t plat_get_my_entrypoint (void);
-	 *
-	 * Main job of this routine is to distinguish between a cold and a warm
-	 * boot.
-	 *
-	 * This functions returns:
-	 *  - 0 for a cold boot.
-	 *  - Any other value for a warm boot.
-	 * ---------------------------------------------------------------------
-	 */
-func plat_get_my_entrypoint
-	/* TODO: support warm boot */
-	mov	x0, #0
-	ret
-endfunc plat_get_my_entrypoint
-
-	/* ---------------------------------------------
-	 * void platform_mem_init (void);
-	 *
-	 * No need to carry out any memory initialization.
-	 * ---------------------------------------------
-	 */
-func platform_mem_init
-	ret
-endfunc platform_mem_init
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_init(void)
-	 * Function to initialize the crash console
-	 * without a C Runtime to print crash report.
-	 * Clobber list : x0 - x3
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_init
-	mov_imm	x0, PLAT_RPI_MINI_UART_BASE
-	mov	x1, xzr
-	mov	x2, xzr
-	b	console_16550_core_init
-endfunc plat_crash_console_init
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_putc(int c)
-	 * Function to print a character on the crash
-	 * console without a C Runtime.
-	 * Clobber list : x1, x2
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_putc
-	mov_imm	x1, PLAT_RPI_MINI_UART_BASE
-	b	console_16550_core_putc
-endfunc plat_crash_console_putc
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_flush()
-	 * Function to force a write of all buffered
-	 * data that hasn't been output.
-	 * Out : return -1 on error else return 0.
-	 * Clobber list : x0, x1
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_flush
-	mov_imm	x0, PLAT_RPI_MINI_UART_BASE
-	b	console_16550_core_flush
-endfunc plat_crash_console_flush
-
-	/* ---------------------------------------------
-	 * void plat_reset_handler(void);
-	 * ---------------------------------------------
-	 */
-func plat_reset_handler
-	/* ------------------------------------------------
-	 * Set L2 read/write cache latency:
-	 * - L2 Data RAM latency: 3 cycles (0b010)
-	 * - L2 Data RAM setup: 1 cycle (bit 5)
-	 * ------------------------------------------------
-	 */
-	mrs	x0, CORTEX_A72_L2CTLR_EL1
-	mov	x1, #0x22
-	orr	x0, x0, x1
-	msr	CORTEX_A72_L2CTLR_EL1, x0
-	isb
-
-	ret
-endfunc plat_reset_handler
diff --git a/plat/rpi/rpi4/include/platform_def.h b/plat/rpi/rpi4/include/platform_def.h
index 6f6bbbe7a..d03eea6e9 100644
--- a/plat/rpi/rpi4/include/platform_def.h
+++ b/plat/rpi/rpi4/include/platform_def.h
@@ -24,7 +24,7 @@
 #define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
 #define PLATFORM_CORE_COUNT		PLATFORM_CLUSTER0_CORE_COUNT
 
-#define RPI4_PRIMARY_CPU		U(0)
+#define RPI_PRIMARY_CPU			U(0)
 
 #define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL1
 #define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CLUSTER_COUNT + \
diff --git a/plat/rpi/rpi4/platform.mk b/plat/rpi/rpi4/platform.mk
index 49e78dfed..0744bceb4 100644
--- a/plat/rpi/rpi4/platform.mk
+++ b/plat/rpi/rpi4/platform.mk
@@ -16,7 +16,7 @@ PLAT_BL_COMMON_SOURCES	:=	drivers/ti/uart/aarch64/16550_console.S	\
 				${XLAT_TABLES_LIB_SRCS}
 
 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a72.S		\
-				plat/rpi/rpi4/aarch64/plat_helpers.S	\
+				plat/rpi/common/aarch64/plat_helpers.S	\
 				plat/rpi/rpi4/aarch64/armstub8_header.S	\
 				drivers/arm/gic/common/gic_common.c     \
 				drivers/arm/gic/v2/gicv2_helpers.c      \