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| author | Peng Fan <peng.fan@nxp.com> | 2020-08-21 10:47:17 +0800 |
|---|---|---|
| committer | Peng Fan <van.freenix@gmail.com> | 2020-09-14 02:35:50 +0000 |
| commit | 093ba62e14099ab4bd9c2452044d19e3589925d6 (patch) | |
| tree | d2c69f685c9d3af06ec209b93c2e06bbd4f8792f /docs | |
| parent | 34029d01c6effbbd643413b69c851cc24d047eaa (diff) | |
doc: Correct CPACR.FPEN usage
To avoid trapping from EL0/1, FPEN bits need to be set 0x3, not
clearing.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: Ic34e9aeb876872883c5f040618ed6d50f21dacd0
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/design/firmware-design.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst index a357d5858..c12e73f45 100644 --- a/docs/design/firmware-design.rst +++ b/docs/design/firmware-design.rst @@ -369,7 +369,7 @@ Architectural initialization For AArch64, BL2 performs the minimal architectural initialization required for subsequent stages of TF-A and normal world software. EL1 and EL0 are given -access to Floating Point and Advanced SIMD registers by clearing the +access to Floating Point and Advanced SIMD registers by setting the ``CPACR.FPEN`` bits. For AArch32, the minimal architectural initialization required for subsequent |