diff options
| author | Pankaj Gupta <pankaj.gupta@nxp.com> | 2020-10-06 00:10:24 +0530 |
|---|---|---|
| committer | Pankaj Gupta <pankaj.gupta@nxp.com> | 2020-11-25 18:52:45 +0530 |
| commit | cc686c94819fdb65bff6feb81fcbf74b07323322 (patch) | |
| tree | bc9198687fda3779d0a0616baa6e233ee1487593 | |
| parent | e26628ec615c66725526ff214c3b0f41b5466661 (diff) | |
nxp:add qspi driver
NXP QuadSPI driver support NXP SoC.
- Supporting QSPI flash
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I928cbec8ea31f4d8f9e320ac9c5105f7ab0ecb73
| -rw-r--r-- | drivers/nxp/qspi/qspi.c | 29 | ||||
| -rw-r--r-- | drivers/nxp/qspi/qspi.h | 31 | ||||
| -rw-r--r-- | drivers/nxp/qspi/qspi.mk | 28 |
3 files changed, 88 insertions, 0 deletions
diff --git a/drivers/nxp/qspi/qspi.c b/drivers/nxp/qspi/qspi.c new file mode 100644 index 000000000..c92bab488 --- /dev/null +++ b/drivers/nxp/qspi/qspi.c @@ -0,0 +1,29 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include <assert.h> + +#include <common/debug.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <qspi.h> + +int qspi_io_setup(uintptr_t nxp_qspi_flash_addr, + size_t nxp_qspi_flash_size, + uintptr_t fip_offset) +{ + uint32_t qspi_mcr_val = qspi_in32(CHS_QSPI_MCR); + + /* Enable and change endianness of QSPI IP */ + qspi_out32(CHS_QSPI_MCR, (qspi_mcr_val | CHS_QSPI_64LE)); + + /* Adding QSPI Memory Map in XLAT Table */ + mmap_add_region(nxp_qspi_flash_addr, nxp_qspi_flash_addr, + nxp_qspi_flash_size, MT_MEMORY | MT_RW); + + return 0; +} diff --git a/drivers/nxp/qspi/qspi.h b/drivers/nxp/qspi/qspi.h new file mode 100644 index 000000000..ba69c552f --- /dev/null +++ b/drivers/nxp/qspi/qspi.h @@ -0,0 +1,31 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __QSPI_H__ +#define __QSPI_H__ + +#include <endian.h> +#include <lib/mmio.h> + +#define CHS_QSPI_MCR 0x01550000 +#define CHS_QSPI_64LE 0xC + +#ifdef NXP_QSPI_BE +#define qspi_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) +#define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) +#elif defined(NXP_QSPI_LE) +#define qspi_in32(a) mmio_read_32((uintptr_t)(a)) +#define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), (v)) +#else +#error Please define CCSR QSPI register endianness +#endif + +int qspi_io_setup(uintptr_t nxp_qspi_flash_addr, + size_t nxp_qspi_flash_size, + uintptr_t fip_offset); + +#endif /* __QSPI_H__ */ diff --git a/drivers/nxp/qspi/qspi.mk b/drivers/nxp/qspi/qspi.mk new file mode 100644 index 000000000..3e2c7350a --- /dev/null +++ b/drivers/nxp/qspi/qspi.mk @@ -0,0 +1,28 @@ +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +# + +ifeq (${QSPI_ADDED},) + +QSPI_ADDED := 1 + +QSPI_DRIVERS_PATH := ${PLAT_DRIVERS_PATH}/qspi + +QSPI_SOURCES := $(QSPI_DRIVERS_PATH)/qspi.c + +PLAT_INCLUDES += -I$(QSPI_DRIVERS_PATH) + +ifeq (${BL_COMM_QSPI_NEEDED},yes) +BL_COMMON_SOURCES += ${QSPI_SOURCES} +else +ifeq (${BL2_QSPI_NEEDED},yes) +BL2_SOURCES += ${QSPI_SOURCES} +endif +ifeq (${BL31_QSPI_NEEDED},yes) +BL31_SOURCES += ${QSPI_SOURCES} +endif +endif + +endif |