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| author | Jiafei Pan <jiafei.pan@nxp.com> | 2021-01-28 05:21:29 +0100 |
|---|---|---|
| committer | Jiafei Pan <jiafei.pan@nxp.com> | 2021-01-28 05:21:29 +0100 |
| commit | a8ed9c72d3c41e1113ad32fa790991c4b1bea5a2 (patch) | |
| tree | e780f0930ff732817d76e52a0e4952cd610515cc | |
| parent | 09d7e5bdf29074528a454ac95f87f7c7f24114fc (diff) | |
| parent | 1271e77538429ba33fed0a1d95aafb6b1cc6d3e9 (diff) | |
Pull request #9: nxp: soc-ls1046: fix errata workaround applying
Merge in LFAC/atf-nxp from ~NXA07204/atf-nxp:ls_v2.4 to lf_v2.4
* commit '1271e77538429ba33fed0a1d95aafb6b1cc6d3e9':
nxp: soc-ls1046: fix errata workaround applying
| -rw-r--r-- | plat/nxp/soc-ls1046/erratas_soc.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/plat/nxp/soc-ls1046/erratas_soc.c b/plat/nxp/soc-ls1046/erratas_soc.c index b84931687..bd26c4174 100644 --- a/plat/nxp/soc-ls1046/erratas_soc.c +++ b/plat/nxp/soc-ls1046/erratas_soc.c @@ -7,10 +7,15 @@ #include <cci.h> #include <mmio.h> +#include <soc_default_base_addr.h> +#include <ls_interconnect.h> +#include <plat_common.h> +#include <dcfg.h> +#include <scfg.h> void erratum_a008850_early(void) { -#ifdef ERRATA_PLAT_A008850 +#ifdef ERRATA_SOC_A008850 /* part 1 of 2 */ uintptr_t cci_base = NXP_CCI_ADDR; uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG); @@ -24,7 +29,7 @@ void erratum_a008850_early(void) void erratum_a008850_post(void) { -#ifdef ERRATA_PLAT_A008850 +#ifdef ERRATA_SOC_A008850 /* part 2 of 2 */ uintptr_t cci_base = NXP_CCI_ADDR; uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG); @@ -42,7 +47,7 @@ void erratum_a008850_post(void) void erratum_a010539(void) { -#ifdef ERRATA_PLAT_A010539 +#ifdef ERRATA_SOC_A010539 #if POLICY_OTA /* * For POLICY_OTA Bootstrap, BOOT_DEVICE_EMMC is used to get FIP and @@ -57,8 +62,8 @@ void erratum_a010539(void) uint32_t val; val = (gur_in32(porsr1) & ~PORSR1_RCW_MASK); - out_be32((void *)(NXP_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1_OFFSET), val); - out_be32((void *)(NXP_SCFG_ADDR + 0x1a8), 0xffffffff); + gur_out32((void *)(NXP_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1_OFFSET), val); + scfg_out32((void *)(NXP_SCFG_ADDR + 0x1a8), 0xffffffff); } #endif |