diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-04-07 15:08:03 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2020-11-18 09:12:32 +0800 |
| commit | 42fa20c724cd357689f9f61cdd655185d88316d5 (patch) | |
| tree | b06a97608c2188d34fa928830c613f3d61353f1e | |
| parent | 5ca6f49f608d1d5f78e6d7810359398021c73216 (diff) | |
MLK-23752 plat: imx8m: Update the src gpr used for imx8mp lpa
On i.MX8MP, the SRC GPR9(0x94) is used by memory repair, so choose
SRC GPR10(0x98) as the LPA status sync register. Add use '==' instead
of '&' for LPA active statue check.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
| -rw-r--r-- | plat/imx/imx8m/gpc_common.c | 3 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mm/include/platform_def.h | 1 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mn/include/platform_def.h | 1 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mp/include/platform_def.h | 1 |
4 files changed, 4 insertions, 2 deletions
diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c index 26d36404a..5d2284fb1 100644 --- a/plat/imx/imx8m/gpc_common.c +++ b/plat/imx/imx8m/gpc_common.c @@ -28,7 +28,6 @@ DEFINE_BAKERY_LOCK(gpc_lock); #define M4_LPA_ACTIVE 0x5555 #define M4_LPA_IDLE 0x0 -#define LPA_STATUS U(0x94) struct plat_gic_ctx imx_gicv3_ctx; @@ -39,7 +38,7 @@ struct plat_gic_ctx imx_gicv3_ctx; bool imx_m4_lpa_active(void) { - return mmio_read_32(IMX_SRC_BASE + LPA_STATUS) & M4_LPA_ACTIVE; + return mmio_read_32(IMX_SRC_BASE + LPA_STATUS) == M4_LPA_ACTIVE; } bool imx_is_m4_enabled(void) diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h index c4454ed40..92e574216 100644 --- a/plat/imx/imx8m/imx8mm/include/platform_def.h +++ b/plat/imx/imx8m/imx8mm/include/platform_def.h @@ -126,6 +126,7 @@ #define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0) #define IMX_M4_STATUS (IMX_SRC_BASE + SRC_M4RCR) #define IMX_M4_ENABLED_MASK SRC_SCR_M4C_NON_SCLR_RST_MASK +#define LPA_STATUS U(0x94) #define SNVS_LPCR U(0x38) #define SNVS_LPCR_SRTC_ENV BIT(0) diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h index 6ab17a9a3..b6150b496 100644 --- a/plat/imx/imx8m/imx8mn/include/platform_def.h +++ b/plat/imx/imx8m/imx8mn/include/platform_def.h @@ -131,6 +131,7 @@ #define GPR_CM7_CPUWAIT BIT(0) #define IMX_M4_STATUS (IMX_IOMUX_GPR_BASE + IOMUXC_GPR22) #define IMX_M4_ENABLED_MASK GPR_CM7_CPUWAIT +#define LPA_STATUS U(0x94) #define ANAMIX_MISC_CTL U(0x124) diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h index fd5b657a7..4811df26c 100644 --- a/plat/imx/imx8m/imx8mp/include/platform_def.h +++ b/plat/imx/imx8m/imx8mp/include/platform_def.h @@ -146,6 +146,7 @@ #define GPR_CM7_CPUWAIT BIT(0) #define IMX_M4_STATUS (IMX_IOMUX_GPR_BASE + IOMUXC_GPR22) #define IMX_M4_ENABLED_MASK GPR_CM7_CPUWAIT +#define LPA_STATUS U(0x98) #define ANAMIX_MISC_CTL U(0x124) #define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) |