diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-09-25 10:25:15 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2020-11-18 09:12:32 +0800 |
| commit | 1f7c872a5faebc96768c2715156909a51fe39926 (patch) | |
| tree | 07b0737073df9198b4d2970be1a8ed5d02f0e274 | |
| parent | cda573f8843acdcd0a2576a6ddfd3dc93219edc2 (diff) | |
MLK-24914-01 plat: imx8mp: Remove vpu reset & memrepair workaround
The VPU reset & memrepair workaround is only for i.MX8MP
A0 silicon. As the A0 will not be supported anymore, so
drop these workaround
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
| -rw-r--r-- | plat/imx/imx8m/imx8mp/gpc.c | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c index e0eae61fd..d754462d7 100644 --- a/plat/imx/imx8m/imx8mp/gpc.c +++ b/plat/imx/imx8m/imx8mp/gpc.c @@ -267,23 +267,6 @@ void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on) /* set the PGC bit */ mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); - /* - * leave the G1, G2, H1 power domain on until VPUMIX power off, - * otherwise system will hang due to VPUMIX ACK - */ - if (domain_id == VPU_H1 || domain_id == VPU_G1 || domain_id == VPU_G2) { - return; - } - - if (domain_id == VPUMIX) { - mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ | - VPU_G2_PWR_REQ | VPU_H1_PWR_REQ); - - while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & (VPU_G1_PWR_REQ | - VPU_G2_PWR_REQ | VPU_H1_PWR_REQ)) - ; - } - /* power down the domain */ mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); |