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This platform implements a FWU Update Agent.
Signed-off-by: jmarinho <jose.marinho@arm.com>
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Add nor flash drivers for executing in the standalonemm execution
context. This includes driver for block io and fvb protocols.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
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Add a platform specific library for passing information on the nor
flash device on the platform. This includes the number of devices,
their size and base address.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
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With some recent changes in OP-TEE [1] and U-Boot [2] we can compile StMM
and launch it from an OP-TEE secure partition which is mimicking SPM.
There's a number of advantages in this approach. In Arm world SPM,
currently used for dispatching StMM, and SPD used for OP-TEE, are
mutually exclusive. Since there's no application in OP-TEE for managing
EFI variables, this means that one can have a secure OS or secure
variable storage.
By re-using StMM we have EDK2s approved application controlling
variable storage and the ability to run a secure world OS. This also
allows various firmware implementations to adopt EDK2 way of storing
variables (including the FTW implementation), as long as OP-TEE is
available on that given platform (or any other secure OS that can launch
StMM and has a supplicant for handling the RPMB partition).
Another advantage is that OP-TEE has the ability to access an eMMC RPMB
partition to store those variables. This requires a normal world
supplicant, which is implemented in U-Boot currently. The supplicant
picks up the encrypted buffer from OP-TEE and wires it to the eMMC
driver(s). Similar functionality can be added in EDK2 by porting the
supplicant and adapt it to using the native eMMC drivers.
There's is one drawback in using OP-TEE. The current SPM calls need to run
to completion. This contradicts the current OP-TEE RPC call requirements,
used to access the RPMB storage. Thats leads to two different SMC calls for
entering secure world to access StMM.
So let's add support for a platform that compiles StMM and an RPMB
driver that communicates with OP-TEE to read/write the variables.
For anyone interested in testing this there's repo that builds all the
sources and works on QEMU [3].
[1] https://github.com/OP-TEE/optee_os/pull/3973
[2] http://u-boot.10912.n7.nabble.com/PATCH-0-7-v4-EFI-variable-support-via-OP-TEE-td412499.html
[3] https://git.linaro.org/people/ilias.apalodimas/efi_optee_variables.git/
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
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A following patch is adding support for building StMM in order to run it
from OP-TEE.
OP-TEE in combination with a NS-world supplicant can use the RPMB
partition of an eMMC to store EFI variables. The supplicant
functionality is currently available in U-Boot only but can be ported
into EDK2. Assuming similar functionality is added in EDK2, this will
allow any hardware with an RPMB partition to store EFI variables
securely.
So let's add a driver that enables access of the RPMB partition through
OP-TEE. Since the upper layers expect a byte addressable interface,
the driver allocates memory and patches the PCDs, while syncing the
memory/hardware on read/write callbacks.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
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Bridge devices should be marked as producers so that their
children can consume the resources. In linux if this isn't
true then the translation gets ignored and the DMA values
are incorrect. This fixes DMA on all the devices that
need a translation.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>
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Add some additional IORT nodes for the USB & EMMC devices, realistically
we probably only need to have a single node with the lowest AddressSizeLimit
but this is conceptually "cleaner" should anyone actually try and use these
values rather than the _DMA provided ones.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
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The arasan caps registers are no longer being overridden by
the brcm iproc driver, so we should be assuring that the
"High Speed Support" bit 21 is set in the capability
register. This significantly improves the wifi perf
using linux.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
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This patch adds a new description of the board's SD/MMC
interfaces in DSDT table that can work with the newly
introduced support in Linux.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
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This patch enables switching to 1.8V power supply
on the VCCQ rail of the AP807 MMC interface,
which allows to operate at HS400 when booting with
ACPI. Since there are issues with this mode in
EDK2 Xenon SD/MMC driver apply a workaround, that
limits the mode to HS200 by forcing bus width to 4.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
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This patch adds a new description of the board's SD/MMC
interfaces in DSDT table that can work with the newly
introduced support in Linux.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
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This patch enables switching to 1.8V power supply
on the VCCQ rail of the CP0 MMC interface,
which allows to operate at HS200 in EDK2 and when
booting with ACPI.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
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This patch adds a new description of the board's SD/MMC
interfaces in DSDT table that can work with the newly
introduced support in Linux.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
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This patch enables switching to 1.8V power supply
on the VCCQ rail of the CP0 MMC interface,
which allows to operate at HS200 in EDK2 and when
booting with ACPI.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
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As per ACPI 6.3 specification, the DSDT/SSDT table should use revision 2
, so update the revision numbers to 2.
This also fixes https://github.com/pftf/RPi4/issues/94 (FWTS failures).
Testing Done:
- Booted to UEFI Shell and used apciview command to check all ACPI
tables' revision.
- Ran FWTS test and no longer see the ACPI DSDT and SSDT revision
failures. Note that the XSDT revision failure is caused by the FWTS
tool's issue that got fixed in
commit c522bfedc9839a474b8d590ba36bec77436d2e90
Cc: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Cc: Jeremy Linton <jeremy.linton@arm.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Signed-off-by: Sunny Wang <sunny.wang@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>
Tested-by: Pete Batard <pete@akeo.ie> # Windows 10 boot
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Convert SsdtThermal.asl to CR/LF like the rest of the sources.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
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Add new SMBIOS Type 32 boot information and Type 3 chassis status
functions that have been added to OemMiscLib in ArmPkg.
Since this is a virtual platform, return fixed values for the chassis
statuses.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Graeme Gregory <graeme@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3332
Currently Fitgen tools verifies every detail of ACM header,
so any ACM header change breaks the tool.
As ACM header is verified by microcode and
ACM itself, Fitgen tool does not need to verify
every fieldof ACM header except some important
fields like ACM_TYPE/SUB_TYPE etc.The changes will
remove the dependency between future ACM header changeand
FitGen tool.
Signed-off-by: Mohammad Miazi <mohammad.m.miazi@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
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This patch registers a virtio net device for Morello
FVP platform.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch adds Readme.md file for Morello Platform.
The document consists of information regarding the platform,
steps to build and boot till UEFI Shell on the Morello FVP
Platform.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch adds the initial support for Morello FVP platform.
Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch implements the configuration manager for Morello
platform. It enables support for generating the following
ACPI tables for Morello FVP Platform:
1. FADT
2. DSDT
3. GTDT
4. MADT
5. SPCR
6. DBG2
7. PPTT
8. IORT
9. MCFG
10. SSDT
Structures have been created to add Common Platform information
and FVP/Testchip platform specific information so that the
same Dxe is usable for all variants of the platform.
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch adds the PlatformDxe Driver for Morello
platform. It includes the registration of the ramdisk
device.
Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Morello FVP platform supports a PCIe root complex.
This patch implements PciHostBridgeLib to support PCIe.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch adds initial Morello Platform Library support.
It includes virtual memory map and helper functions for
platform initialization.
Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Because of the limitation in a number of available intterrupts
that can be mapped in a current version of the IcuLib,
the ACPI support for Cn9132 variant remained disabled.
Such hard limitation is not needed though and enable ACPI
boot, however with a the interfaces present only on the
first two CP115 HW blocks.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
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The ACPI tables of MacchiatoBin board were missing 2.5G
NIC port description. Add it.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
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The early firmware allows to use flow control mechanism via
shared memory region. Include its description in the PP2
NIC nodes.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
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One of first logs visible during DXE initialization is a fixed
string "Armada Platform Init", which is pretty generic and not
true for CN913X platforms. Modify it to use already existing
vendor/product name PCDs.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
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Following the Ecc reported error in the edk2 repository,
the SCMI_CLOCK_RATE structure has been modified in:
an enum and its elements have been renamed in:
ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
This patch is a follow-up and fixes the following Ecc
reported error:
Complex types should be typedef-ed
The error is due to the a nested structure declaration.
The patch also re-formats the debug messages to fit in
a 80 chars line.
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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edk2-non-osi project is a more proper place for keeping
the device tree sources, so move it there. It is a preparation
for the DT upgrade for the Armada 7k8k SoC family.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
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This is a fix for https://github.com/pftf/RPi4/issues/114.
Changes:
1. Add a setup option called BootPolicy and consume the setting
during boot to decide whether to perform or skip ConnectAll.
2. The Default setting is set to Full discovery because it is not
worth enabling Fast boot by default on RaspberryPi systems.
Enabling it just saves boot time about 1 second, but caused a
lot of issues.
Testing Done:
- Booted to Standalone UEFI shell on SD card and use drivers
command to check the result with Fast Boot and Full discovery
settings. Then, child/device handles are created as expected.
Note and to-do items:
- The root cause looks like that boot loaders and some tools like
grub and iPXE haven't supported selective connect/Fast boot.
However, system firmware should still provide a setup option for
user to enable Fast boot with old version boot loaders and tools,
which is why we proposed this change. We will also report this
issue to boot loader and tool vendors/open source GitHubs.
- We will add more options for connecting specific type devices so
that we can still have the shortest boot time for all use cases.
Cc: Jeremy Linton <jeremy.linton@arm.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Link: https://github.com/pftf/RPi4/issues/144
Link: https://github.com/pftf/RPi4/issues/114
Signed-off-by: Sunny Wang <sunny.wang@arm.com>
Acked-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>
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Add PCDs for base address and address space size for generic timer and
SMMU controllers. Use those PCDs to add platform memory map entries. The
ServerReady SBSA tests, when executed, accesses these controllers and so
the memory mapping for generic timer and SMMU controllers are required.
In addition to this, PCDs for watchdog timer controller base address and
size are introduced instead of using macros for the same. This allows
the base address and address space size for watchdog timer controller to
be specified by platform description files.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The generic timer and watchdog timer interrupt numbers on the RD-N2
platform is different than those on the other platforms supported by
SgiPkg. So in order to reuse the existing GTDT ACPI table for all the
supported platforms including RD-N2, introduce and use PCD to provide
the interrupt numbers for watchdog and generic timers.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Fix the ACPI DSDT/SSDT table version numbers. As per ACPI 6.3
specification, the DSDT/SSDT table should use version 2 instead of 1. In
addition to this, update 'PcdAcpiExposedTableVersions' to avoid building
RSDT table into ACPI firmware volume because the platforms supported
under SgiPkg are 64-bit systems only and require only the XSDT table.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Fix the incorrect ACPI _UID (Unique ID) object for CPU devices listed
for the RD-V1-MC platform.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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RD-V1-MC platform has four CPUs in each of its four coherently connected
chips. So remove a incorrect CPU device entry in DSDT table that lists a
additional non-existent CPU.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Ssdt ACPI table in SgiPkg describes the PCIe controller and the root
complex resources. Include this table for RD-V1 and RD-V1-MC platforms.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The commit 7e4c6f982a0accd5aa86337b46d20199db989aeb
updated ShadowMicrocode module to consume MicrocodeLib.
But the change caused the build failure.
The patch fixed the build failure and the functionality was
verified in real platform.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
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The NULL instance of BoardAcpiTableLib in MinPlatformPkg currently
has a few organization issues that make it more difficult to find
and use than a typical NULL library instance.
1. It shares a directory with another unrelated library instance.
2. The directory name "BoardAcpiLibNull" is not directly related to
either library instance name in the directory.
3. The library instance has unnecessary dependencies.
4. The BASE_NAME does not indicate the library instance is the NULL
instance.
5. The C source file name does not match the INF file name making
finding the C source by search more cumbersome than needed.
This change resolves the above issues to improve use and
maintainability.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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The NULL instance of BoardAcpiEnableLib in MinPlatformPkg currently
has a few organization issues that make it more difficult to find
and use than a typical NULL library instance.
1. It shares a directory with another unrelated library instance.
2. The directory name "BoardAcpiLibNull" is not directly related to
either library instance name in the directory.
3. The library instance has unnecessary dependencies.
4. The BASE_NAME does not indicate the library instance is the NULL
instance.
5. The C source file name does not match the INF file name making
finding the C source by search more cumbersome than needed.
This change resolves the above issues to improve maintainability.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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LargeVariableWriteLib is used to store large data sets using
the UEFI Variable Services. At time of writting, most UEFI
Variable Services implementations to not allow more than 64KB
of data to be stored in a single UEFI variable. This library
will split data sets across multiple variables as needed.
It adds the SetLargeVariable() API to provide this service.
The primary use for this library is to create binary compatible
drivers and OpROMs which need to work both with TianoCore and
other UEFI PI implementations. When customizing and recompiling
the platform firmware image is possible, adjusting the value of
PcdMaxVariableSize may provide a simpler solution to this
problem.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
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LargeVariableReadLib is used to retrieve large data sets using
the UEFI Variable Services. At time of writting, most UEFI
Variable Services implementations to not allow more than 64KB
of data to be stored in a single UEFI variable. This library
will split data sets across multiple variables as needed.
It adds the GetLargeVariable() API to provide this service.
The primary use for this library is to create binary compatible
drivers and OpROMs which need to work both with TianoCore and
other UEFI PI implementations. When customizing and recompiling
the platform firmware image is possible, adjusting the value of
PcdMaxVariableSize may provide a simpler solution to this
problem.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
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VariableWriteLib is a phase agnostic library for writing
to UEFI Variables. This library provides the MinSetVariable(),
MinQueryVariableInfo(), MinIsVariableRequestToLockSupported(),
and MinVariableRequestToLock() APIs which are usable in DXE
and SMM.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
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VariableReadLib is a phase agnostic libary for reading UEFI
Variables. This library provides the
MinGetVariable() and MinGetNextVariableName() APIs which
are usable PEI, DXE, and SMM.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
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Add PcdMicrocodeOffsetInFv in MinPlatformPkg.dec and update
SecFspWrapperPlatformSecLib library to use the microcode location
PCDs defined in MinPlatformPkg.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
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Update SMBIOS Type 4 field name from ProcessorManufacture to
ProcessorManufacturer to match latest SMBIOS include file
definitions in MdePkg.
Cc: Zailiang Sun <zailiang.sun@intel.com>
Cc: Yi Qian <yi.qian@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Zailiang Sun <zailiang.sun@intel.com>
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Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Reviewed-by: Siyuan Fu <siyuan.fu@intel.com>
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Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Zailiang Sun <zailiang.sun@intel.com>
Cc: Yi Qian <yi.qian@intel.com>
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