diff options
| author | Marcin Wojtas <mw@semihalf.com> | 2021-03-27 09:21:26 +0100 |
|---|---|---|
| committer | Ard Biesheuvel <ardb@kernel.org> | 2021-05-10 18:06:24 +0200 |
| commit | 34d0014340a6e27e6135d17061e96b8c41df145a (patch) | |
| tree | 9fc8f86a2c21ad89a2e9baa22e50f081992a3e72 | |
| parent | 02bb0f73641c4ae0e771773e5a9915c2282c47b3 (diff) | |
Marvell/Cn913xDb: Update AP807 MMC settings
This patch enables switching to 1.8V power supply
on the VCCQ rail of the AP807 MMC interface,
which allows to operate at HS400 when booting with
ACPI. Since there are issues with this mode in
EDK2 Xenon SD/MMC driver apply a workaround, that
limits the mode to HS200 by forcing bus width to 4.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
3 files changed, 30 insertions, 2 deletions
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c index 2b46d141..2755600f 100644 --- a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c @@ -95,8 +95,12 @@ MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] = { { /* eMMC 0xF06E0000 */
0, /* SOC will be filled by MvBoardDescDxe */
0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
- FALSE, /* Xenon1v8Enabled */
- TRUE, /* Xenon8BitBusEnabled */
+ TRUE, /* Xenon1v8Enabled */
+ /*
+ * Force 4-bit bus width - work-around for non
+ * functional HS400 mode.
+ */
+ FALSE, /* Xenon8BitBusEnabled */
FALSE, /* XenonSlowModeEnabled */
0x40, /* XenonTuningStepDivisor */
EmbeddedSlot /* SlotType */
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c index 42dc54a8..965d8efe 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c @@ -157,6 +157,27 @@ Cp2XhciInit ( MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER);
}
+STATIC CONST MV_GPIO_PIN mApSdMmcPins[] = {
+ {
+ MV_GPIO_DRIVER_TYPE_PCA95XX,
+ CN9130_DB_IO_EXPANDER0,
+ CN9130_DB_AP_MMC_VCCQ_PIN,
+ TRUE,
+ },
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+ApSdMmcInit (
+ IN NON_DISCOVERABLE_DEVICE *This
+ )
+{
+ return ConfigurePins (mApSdMmcPins,
+ ARRAY_SIZE (mApSdMmcPins),
+ MV_GPIO_DRIVER_TYPE_PCA95XX);
+}
+
STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] = {
{
MV_GPIO_DRIVER_TYPE_PCA95XX,
@@ -206,6 +227,8 @@ NonDiscoverableDeviceInitializerGet ( if (Type == NonDiscoverableDeviceTypeSdhci) {
switch (Index) {
+ case 0:
+ return ApSdMmcInit;
case 1:
return Cp0SdMmcInit;
}
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h index a641420e..00449d43 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h @@ -13,6 +13,7 @@ #define CN9130_DB_VBUS0_LIMIT_PIN 4
#define CN9130_DB_VBUS1_PIN 1
#define CN9130_DB_VBUS1_LIMIT_PIN 5
+#define CN9130_DB_AP_MMC_VCCQ_PIN 8
#define CN9130_DB_SDMMC_VCC_PIN 14
#define CN9130_DB_SDMMC_VCCQ_PIN 15
#define CN9131_DB_VBUS0_PIN 3
|