diff options
| author | Wasim Khan <wasim.khan@nxp.com> | 2020-05-26 14:07:15 +0530 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@arm.com> | 2020-05-26 11:45:54 +0200 |
| commit | 1212c5177a3f15ba0d593b291b2349af6e212121 (patch) | |
| tree | 2e4cc554a9c6e8c6f9e309b858806f32d636bfe0 | |
| parent | 9bbe2e2d75c839e7e44fc37300d1fc44204f9bef (diff) | |
Silicon/NXP: PciSegmentLib: Add ECAM config support for PCIe LS Controller
PCIe Layerscape controller can be enabled for ECAM style
configuration access using CFG SHIFT Feature.
Check for PcdPciCfgShiftEnable to decide the configuration access
scheme to be used with PCIe LS controller.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
| -rwxr-xr-x | Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 21 | ||||
| -rwxr-xr-x | Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf | 3 |
2 files changed, 20 insertions, 4 deletions
diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c index d0bacca3..68b6209c 100755 --- a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c @@ -34,6 +34,8 @@ typedef enum { #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
+STATIC BOOLEAN CfgShiftEnable;
+
STATIC
UINT64
PciLsCfgTarget (
@@ -88,11 +90,21 @@ PciLsGetConfigBase ( {
UINT32 CfgAddr;
- CfgAddr = (UINT16)Offset;
- if (Bus > 0) {
- return PciLsCfgTarget (PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment, Address, Segment, Bus, Offset);
+ if (CfgShiftEnable) {
+ CfgAddr = (UINT32)Address;
+ if (Bus > 0) {
+ return PCI_SEG0_MMIO_MEMBASE + PCI_BASE_DIFF * Segment + CfgAddr;
+ } else {
+ return PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment + CfgAddr;
+ }
} else {
- return PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment + CfgAddr;
+ CfgAddr = (UINT16)Offset;
+ if (Bus > 0) {
+ return PciLsCfgTarget (PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment,
+ Address, Segment, Bus, Offset);
+ } else {
+ return PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment + CfgAddr;
+ }
}
}
@@ -608,5 +620,6 @@ PciSegLibInit ( IN EFI_SYSTEM_TABLE *SystemTable
)
{
+ CfgShiftEnable = CFG_SHIFT_ENABLE;
return EFI_SUCCESS;
}
diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf index a36e7923..936213dc 100755 --- a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf @@ -30,3 +30,6 @@ [FixedPcd]
gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable
|