hisi_sas: add device tree binding and MAINTAINERS

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: flyingnosky <flyingnosky@163.com>

1 files changed, 78 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
new file mode 100644
index 000000000000..3eb63a4402d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
@@ -0,0 +1,78 @@
+* HiSilison SAS controller
+
+The HiSilicon SAS controller consists of a number of independent SAS cores.
+Each core is based on the same IP, but each instance of a SAS core in HW
+may be configured differently.
+
+Main node required properties:
+  - compatible : value should be as follows:
+	(a) "hisilicon,sas-controller" for HiSilicon SAS controller IP
+
+  - core-count : the number of SAS cores in the controller
+
+SAS core sub-node properties:
+  - compatible : value should be as follows:
+	(a) "hisilicon,sas-core-v1" for v1 of HiSilicon SAS core IP
+	(a) "hisilicon,sas-core-v2" for v2 of HiSilicon SAS core IP
+
+  - core-id : identifier for core in Soc
+
+  - reg : Address and length of the register sets for the device
+   - SAS core registers
+   - SAS core control registers
+
+  - reset-reg : offset to reset register in control registers
+
+  - queue-count : number of delivery and completion queues in the core
+
+  - phy-count : number of phys accessible by the core
+
+  - interrupts : Interrupts for phys, completion queues, and fatal
+		 interrupts:
+		  - Each phy has 4 interrupt sources:
+			- broadcast
+			- phyup
+			- abnormal
+			- reg set 1 interrupts
+		  - Each completion queue has 1 interrupt source
+		  - Each core has 2 fatal interrupt sources:
+			- ECC
+			- AXI bus
+
+Example:
+	hisi_sas: sas {
+		compatible = "hisilicon,sas-controller";
+		core-count = <2>;
+		status = "okay";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		#interrupt-cells = <2>;
+		dma-coherent;
+		ranges;
+
+		core0: sas@0xc1000000 {
+			compatible = "hisilicon,sas-core-v1";
+			core-id = <0>;
+			reg = <0x0 0xc1000000 0x0 0x10000>,
+				<0x0 0xc0000000 0x0 0x10000>;
+			reset-reg = <0xa60>;
+			queue-count = <32>;
+			phy-count = <8>;
+			interrupt-parent = <&mbigen_dsa>;
+			interrupts = <259 4>,<263 4>,<264 4>,<265 4>,
+					<269 4>,<273 4>,<274 4>,<275 4>,
+					<279 4>,<283 4>,<284 4>,<285 4>,
+					<289 4>,<293 4>,<294 4>,<295 4>,
+					<299 4>,<303 4>,<304 4>,<305 4>,
+					<309 4>,<313 4>,<314 4>,<315 4>,
+					<319 4>,<323 4>,<324 4>,<325 4>,
+					<329 4>,<333 4>,<334 4>,<335 4>,
+					<336 1>,<337 1>,<338 1>,<339 1>,<340 1>,<341 1>,<342 1>,<343 1>,
+					<344 1>,<345 1>,<346 1>,<347 1>,<348 1>,<349 1>,<350 1>,<351 1>,
+					<352 1>,<353 1>,<354 1>,<355 1>,<356 1>,<357 1>,<358 1>,<359 1>,
+					<360 1>,<361 1>,<362 1>,<363 1>,<364 1>,<365 1>,<366 1>,<367 1>,
+					<376 4>,
+					<381 4>;
+			status = "okay";
+		};
+	};