diff options
| author | Zhou Wang <wangzhou1@hisilicon.com> | 2015-10-10 14:17:25 +0800 |
|---|---|---|
| committer | Sherlock Wang <sherlock.wang@139.com> | 2015-11-06 15:51:17 +0800 |
| commit | ce84281a127fe3a2ce519bd5b6234a976e0ce813 (patch) | |
| tree | badce5b83ce26a95d76acc611bcaff7e010aaf3d | |
| parent | d1f7b3ca19acf80e411ed7f6a050d606549b089c (diff) | |
PCI: hisi: Bypass SMMU for Hip06 PCIe controller
SMMU only allocates memory for stream ID 0, however, stream ID sent to SMMU by
PCIe controller is BDF of PCIe device, which will bring error. So this patch
set Hip06 PCIe controller to bypass SMMU.
Signed-off-by: Zhenfa Qiu <qiuzhenfa@hisilicon.com>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
| -rw-r--r-- | drivers/pci/host/pcie-hisi-hip06.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/pci/host/pcie-hisi-hip06.c b/drivers/pci/host/pcie-hisi-hip06.c index 4efc6d443a55..7deb2b4b3701 100644 --- a/drivers/pci/host/pcie-hisi-hip06.c +++ b/drivers/pci/host/pcie-hisi-hip06.c @@ -17,11 +17,15 @@ #include "pcie-designware.h" #include "pcie-hisi.h" - #define HIP06_PCIE_CLK_CTRL 0x7 #define HIP06_PCS_SERDES_STATUS 0x504 #define HIP06_PCIE_CORE_RESET 0x3 +#define PCIE_SYS_CTRL_13_REG 0x4 +#define PCIE_MST_BYPASS_SMMU_EN BIT(10) +#define PCIE_MST_AW_BYPASS_SMMU_EN BIT(12) +#define PCIE_MST_AR_BYPASS_SMMU_EN BIT(13) + /*Check if the link is up*/ static int hisi_pcie_link_up_hip06(struct hisi_pcie *pcie) { @@ -100,7 +104,19 @@ void pcie_equalization_hip06(struct hisi_pcie *pcie) static void hisi_pcie_mode_set_hip06(struct hisi_pcie *pcie) { + u32 val; + hisi_pcie_ctrl_writel(pcie, 0x4 << 28, PCIE_CORE_MODE_REG); + + /* + * bypass SMMU. SMMU only allocates memory for stream ID 0, however, + * stream ID sent to SMMU by PCIe controller is BDF of PCIe device, + * which will bring error. + */ + val = hisi_pcie_ctrl_readl(pcie, PCIE_SYS_CTRL_13_REG); + val |= PCIE_MST_BYPASS_SMMU_EN | PCIE_MST_AW_BYPASS_SMMU_EN | + PCIE_MST_AR_BYPASS_SMMU_EN; + hisi_pcie_ctrl_writel(pcie, val, PCIE_SYS_CTRL_13_REG); } static void hisi_pcie_portnum_set_hip06(struct hisi_pcie *pcie, u32 num) |