diff options
| author | Gabriele Paoloni <gabriele.paoloni@huawei.com> | 2015-09-29 22:47:35 +0800 |
|---|---|---|
| committer | Sherlock Wang <sherlock.wang@139.com> | 2015-11-06 15:51:17 +0800 |
| commit | babe530ccfa1dde23e88582c8ce5bd762d0a349f (patch) | |
| tree | 75d570f8a0781c808e953848420bfd2f6df75838 | |
| parent | b733945ba7e52793ef94c7f8005b39650d25a075 (diff) | |
PCI: hisi: pass msi controller address by DT
This patch reworks the code in order to get the
address of the MSI controller from DT.
This is needed to make the code cleaner as we are
going to support multiple SoCs
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
| -rwxr-xr-x[-rw-r--r--] | drivers/pci/host/pcie-hisi.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c index f2ad00bcf012..bdb6b0a4ddc3 100644..100755 --- a/drivers/pci/host/pcie-hisi.c +++ b/drivers/pci/host/pcie-hisi.c @@ -17,6 +17,7 @@ #include <linux/of.h> #include <linux/of_pci.h> #include <linux/platform_device.h> +#include <linux/of_address.h> #include "pcie-designware.h" @@ -34,7 +35,7 @@ #define PCIE_MSI_TRANS_REG 0x1c8 #define PCIE_MSI_LOW_ADDRESS 0x1b4 #define PCIE_MSI_HIGH_ADDRESS 0x1c4 -#define PCIE_MSI_ADDRESS_VAL 0xb7010040 +#define PCIE_GITS_TRANSLATER 0x10040 #define PCIE_SYS_CTRL20_REG 0x20 #define PCIE_RD_TAB_SEL BIT(31) @@ -114,6 +115,7 @@ struct hisi_pcie { void __iomem *serdes_base; u32 port_id; struct pcie_port pp; + u64 msi_addr; }; static inline void hisi_pcie_subctrl_writel(struct hisi_pcie *pcie, @@ -223,8 +225,8 @@ static void hisi_pcie_config_context(struct hisi_pcie *pcie) val &= ((~PCIE_RD_TAB_SEL) & (~PCIE_RD_TAB_EN)); hisi_pcie_apb_writel(pcie, val, PCIE_SYS_CTRL20_REG); - hisi_pcie_apb_writel(pcie, PCIE_MSI_ADDRESS_VAL, PCIE_MSI_LOW_ADDRESS); - hisi_pcie_apb_writel(pcie, 0x0, PCIE_MSI_HIGH_ADDRESS); + hisi_pcie_apb_writel(pcie, pcie->msi_addr & 0xffffffff, PCIE_MSI_LOW_ADDRESS); + hisi_pcie_apb_writel(pcie, pcie->msi_addr >> 32, PCIE_MSI_HIGH_ADDRESS); hisi_pcie_apb_writel(pcie, PCIE_MSI_ASID_ENABLE | PCIE_MSI_ASID_VALUE, PCIE_SLV_MSI_ASID); hisi_pcie_apb_writel(pcie, PCIE_MSI_TRANS_ENABLE, PCIE_MSI_TRANS_REG); @@ -664,7 +666,10 @@ static int hisi_pcie_msi_host_init(struct pcie_port *pp, { struct device_node *msi_node; struct irq_domain *irq_domain; + struct resource res; struct device_node *np = pp->dev->of_node; + struct hisi_pcie *pcie = to_hisi_pcie(pp); + msi_node = of_parse_phandle(np, "msi-parent", 0); if (!msi_node) { @@ -672,6 +677,10 @@ static int hisi_pcie_msi_host_init(struct pcie_port *pp, return -ENODEV; } + of_address_to_resource(msi_node, 0, &res); + + pcie->msi_addr = res.start + PCIE_GITS_TRANSLATER; + irq_domain = irq_find_host(msi_node); if (!irq_domain) { dev_err(pp->dev, "failed to find irq domain\n"); |