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authorGabriele Paoloni <gabriele.paoloni@huawei.com>2015-09-29 10:38:39 +0800
committerSherlock Wang <sherlock.wang@139.com>2015-11-06 15:51:17 +0800
commitb733945ba7e52793ef94c7f8005b39650d25a075 (patch)
tree84b1449880e854cf50819954758204ae5beb40c8
parent14694f79fe049c580081aaa0dafbddd628fc8903 (diff)
dts bindings:hisilicon-pcie.txt
add pcie pcs base and serdes base description Signed-off-by: liudongdong <liudongdong3@huawei.com>
-rw-r--r--Documentation/devicetree/bindings/pci/hisilicon-pcie.txt9
1 files changed, 6 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index 2afc9d155899..789be59219a4 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -13,7 +13,9 @@ Required properties:
- reg-names: Must include the following entries:
"rc_dbi": controller configuration registers;
"subctrl": whole PCIe hosts configuration registers;
- "config": PCIe configuration space registers.
+ "pcs": pcs configuration registers;
+ "config": PCIe configuration space registers;
+ "serdes": serdes configuration registers.
- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
- port-id: Should be 0, 1, 2 or 3.
@@ -25,8 +27,9 @@ Example:
pcie@0xb0080000 {
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
reg = <0 0xb0080000 0 0x10000>, <0 0xb0000000 0 0x10000>,
- <0x220 0x00000000 0 0x2000>;
- reg-names = "rc_dbi", "subctrl", "config";
+ <0 0xb00d0000 0 0x10000>, <0x220 0x00000000 0 0x2000>,
+ <0 0xb2000000 0 0x40000>;
+ reg-names = "rc_dbi", "subctrl", "pcs", "config", "serdes";
bus-range = <0 15>;
msi-parent = <&its_pcie>;
#address-cells = <3>;