diff options
| author | Sherlock Wang <sherlock.wang@139.com> | 2015-11-06 16:00:24 +0800 |
|---|---|---|
| committer | Sherlock Wang <sherlock.wang@139.com> | 2015-11-06 16:00:31 +0800 |
| commit | 7405d4efcb889644296751ce7d42661f74c90e8c (patch) | |
| tree | 8ee871058c8dd284b9614d43cb0ea362c9495865 | |
| parent | ce84281a127fe3a2ce519bd5b6234a976e0ce813 (diff) | |
DT: Hip05-d02: add pcie nodes for D02 board
Different boards have different PCIe cpu addresss assigned by DAW(e.g. 1p
server board and D02 board). so here a new dtsi file is added to support pcie
dts nodes of D02.
This is a temporary solution as pcie node should be put under peripherals
node. Obviously we should modify a lot for a formal one.
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hisi_p660_pcie_d02.dtsi | 35 |
2 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts index e69ab395d02b..7a8d4745e5a0 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts @@ -12,6 +12,7 @@ /dts-v1/; /include/ "hip05.dtsi" +/include/ "hisi_p660_pcie_d02.dtsi" / { model = "Hisilicon PhosphorV660 D02 Development Board"; diff --git a/arch/arm64/boot/dts/hisilicon/hisi_p660_pcie_d02.dtsi b/arch/arm64/boot/dts/hisilicon/hisi_p660_pcie_d02.dtsi new file mode 100644 index 000000000000..260407a8437c --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hisi_p660_pcie_d02.dtsi @@ -0,0 +1,35 @@ +/ { + pcie@0xb0080000 { + compatible = "hisilicon,hip05-pcie", "snps,dw-pcie"; + reg = <0 0xb0080000 0 0x10000>, <0 0xb0000000 0 0x10000>, + <0 0xb00d0000 0 0x10000>, <0x220 0x00000000 0 0x2000>; + reg-names = "rc_dbi", "subctrl", "pcs", "config"; + bus-range = <0 127>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + ranges = <0x02000000 0 0xb0000000 0x220 0x00000000 0 0x10000000>; + num-lanes = <8>; + port-id = <1>; + status = "ok"; + }; + + pcie@0xb0090000 { + compatible = "hisilicon,hip05-pcie", "snps,dw-pcie"; + reg = <0 0xb0090000 0 0x10000>, <0 0xb0000000 0 0x10000>, + <0 0xb00e0000 0 0x10000>, <0x240 0x00000000 0 0x2000>; + reg-names = "rc_dbi", "subctrl", "pcs", "config"; + bus-range = <128 255>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + ranges = <0x02000000 0 0xb0000000 0x240 0x00000000 0 0x10000000>; + num-lanes = <8>; + port-id = <2>; + status = "ok"; + }; +}; |