diff options
| author | wangyufen <wangyufen@huawei.com> | 2015-09-29 10:36:46 +0800 |
|---|---|---|
| committer | Sherlock Wang <sherlock.wang@139.com> | 2015-11-06 15:51:15 +0800 |
| commit | 55cb394f576a65f58908dda9c19c014b1acacb4e (patch) | |
| tree | 7cf6ab4298556f7a66eb8ce6dbbd6f13192c60d5 | |
| parent | 63b3d555fa5e6a5bc2ca2941efd4a11a26c4c7a8 (diff) | |
pcie: setting of the Directed Speed Change field
Signed-off-by: Jukuo Zhang <zhangjukuo@huawei.com>
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
| -rw-r--r-- | drivers/pci/host/pcie-designware.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 0cf967a2c35b..16fb86289338 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -843,12 +843,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp) val |= PORT_LOGIC_LINK_WIDTH_8_LANES; break; } - dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); - dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); + /* set the Directed Speed Change field of the + Link Width and Speed Change Control register */ val |= PORT_LOGIC_SPEED_CHANGE; - dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); + dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); + /* setup RC BARs */ dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); |