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authorKefeng Wang <wangkefeng.wang@huawei.com>2015-09-29 10:36:42 +0800
committerSherlock Wang <sherlock.wang@139.com>2015-11-06 15:51:14 +0800
commit269bc46dfbb2228346cad244a7d3b9ec6d8721fc (patch)
tree02d952178d6ef6f419a90911d00621101467cfdd
parent70989383eee60f3f1b9ec2b2f505614048220d38 (diff)
pcie: hisi: bugfix for gen3
To support lsi megaraid 2208 card. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
-rw-r--r--drivers/pci/host/pcie-designware.c8
-rw-r--r--drivers/pci/host/pcie-hisi.c1
2 files changed, 5 insertions, 4 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 2ef0772192ae..14d9e16d965e 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -506,10 +506,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
/* program correct class for RC */
dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
- dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
- val |= PORT_LOGIC_SPEED_CHANGE;
- dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
-
#ifdef CONFIG_ARM64
struct pci_bus *bus;
struct msi_controller *msi;
@@ -841,6 +837,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
}
dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
+ val |= PORT_LOGIC_SPEED_CHANGE;
+ dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
+
/* setup RC BARs */
dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 60105ddcbbb1..e7a44bf95316 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers/pci/host/pcie-hisi.c
@@ -410,6 +410,7 @@ static int hisi_pcie_establish_link(struct pcie_port *pp)
}
}
+ mdelay(800);
dev_info(pp->dev, "Link up\n");
return 0;