/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include "msm-iommu-v1.dtsi"

&soc {
	mdp_iommu_8994: qcom,iommu@fd9cc000 {
		compatible = "qcom,msm-smmu-v1";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		reg = <0xfd9cc000 0x10000>;
		reg-names = "iommu_base";
		interrupts = <0 73 0>,
				<0 229 0>, <0 231 0>,
				<0 230 0>, <0 232 0>;
		interrupt-names = "pmon",
				"global_cfg_NS_irq", "global_client_NS_irq",
				"global_cfg_S_irq", "global_client_S_irq";
		qcom,iommu-secure-id = <1>;
		label = "mdp_iommu";
		qcom,msm-bus,name = "mdp_ebi";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
				<22 512 0 0>,
				<22 512 0 1000>;

		status = "ok";
		vdd-supply = <&gdsc_mdss>;
		clocks = <&clock_mmss clk_mdss_axi_clk>,
			<&clock_mmss clk_mdss_ahb_clk>;
		clock-names = "core_clk", "iface_clk";

		qcom,iommu-pmu-ngroups = <1>;
		qcom,iommu-pmu-ncounters = <8>;
		qcom,iommu-pmu-event-classes = <0x00
						0x01
						0x08
						0x09
						0x0A
						0x10
						0x11
						0x12
						0x80
						0x81
						0x82
						0x83
						0x90
						0x91
						0x92
						0xb0
						0xb1>;

		qcom,iommu-bfb-regs =  <0x2000
					0x204c
					0x2060
					0x2514
					0x2540
					0x256c
					0x20ac
					0x215c
					0x220c
					0x22bc
					0x2314
					0x2394
					0x2414
					0x2494
					0x2008
					0x200c
					0x2010
					0x2014
					0x2018>;

		qcom,iommu-bfb-data =  <0x3
					0x7fffff
					0x1777
					0x0
					0x4
					0x10
					0x5000
					0x182c1
					0x5a1d
					0x1822d
					0x0
					0x0
					0x28
					0x68
					0x0
					0x0
					0x0
					0x0
				0x0>;

		qcom,iommu-ctx@fd9d4000 {
			compatible = "qcom,msm-smmu-v1-ctx";
			reg = <0xfd9d4000 0x1000>;
			interrupts = <0 47 0>;
			qcom,iommu-ctx-sids = <0>;
			label = "mdp_0";
		};

		qcom,iommu-ctx@fd9d5000 {
			compatible = "qcom,msm-smmu-v1-ctx";
			reg = <0xfd9d5000 0x1000>;
			interrupts = <0 47 0>, <0 46 0>;
			qcom,iommu-ctx-sids = <1>;
			label = "mdp_1";
			qcom,secure-context;
		};

		qcom,iommu-ctx@fd9d6000 {
			compatible = "qcom,msm-smmu-v1-ctx";
			reg = <0xfd9d6000 0x1000>;
			interrupts = <0 47 0>, <0 46 0>;
			qcom,iommu-ctx-sids = <>;
			label = "mdp_2";
			qcom,secure-context;
		};
	};
};

&venus_iommu {
	status = "ok";
	vdd-supply = <&gdsc_venus>;
	clocks = <&clock_mmss clk_venus0_axi_clk>,
		<&clock_mmss clk_venus0_ahb_clk>,
		<&clock_mmss clk_venus0_vcodec0_clk>;
	clock-names = "core_clk", "iface_clk", "alt_core_clk";

	qcom,iommu-bfb-regs =  <0x2000
				0x204c
				0x2060
				0x2514
				0x2540
				0x256c
				0x20ac
				0x215c
				0x220c
				0x22bc
				0x2314
				0x2394
				0x2414
				0x2494
				0x2008
				0x200c
				0x2010
				0x2014
				0x2018
				0x201c>;

	qcom,iommu-bfb-data =  <0x3
				0x7ffffff
				0x1555
				0x0
				0x4
				0x8
				0x13607
				0x140a0
				0x4000
				0x14020
				0x0
				0x0
				0x94
				0x114
				0x0
				0x0
				0x0
				0x0
				0x0
				0x0>;

	venus_ns: qcom,iommu-ctx@fdc8c000 {
		qcom,iommu-ctx-sids = <0x00 0x21 0x45 0x47 0x48 0x49 0x4a
					0x4b 0x4c 0x65 0x67 0x69 0x6a 0x6b>;
		qcom,iommu-sid-mask = <0x0 0xf 0x0 0x0 0x0 0x0 0x0
					0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
	};

	venus_sec_bitstream: qcom,iommu-ctx@fdc8d000 {
		qcom,iommu-ctx-sids = <0x400 0x421 0x422 0x423 0x424 0x448
					0x44a 0x46a>;
		label = "venus_sec_bitstream";
	};

	venus_fw: qcom,iommu-ctx@fdc8e000 {
		qcom,iommu-ctx-sids = <0x600 0x606>;
	};

	venus_sec_pixel: qcom,iommu-ctx@fdc8f000 {
		compatible = "qcom,msm-smmu-v1-ctx";
		reg = <0xfdc8f000 0x1000>;
		interrupts = <0 42 0>, <0 43 0>;
		qcom,iommu-ctx-sids = <0x425 0x428 0x445 0x44c 0x465>;
		label = "venus_sec_pixel";
		qcom,secure-context;
	};

	venus_sec_non_pixel: qcom,iommu-ctx@fdc90000 {
		compatible = "qcom,msm-smmu-v1-ctx";
		reg = <0xfdc90000 0x1000>;
		interrupts = <0 42 0>, <0 43 0>;
		qcom,iommu-ctx-sids = <0x427 0x447 0x449 0x44b 0x467 0x469 0x46b
					0x500>;
		label = "venus_sec_non_pixel";
		qcom,secure-context;
	};
};

&jpeg_iommu {
	status = "ok";
	vdd-supply = <&gdsc_jpeg>;
	qcom,needs-alt-core-clk;
	qcom,needs-alt-iface-clk;
	clocks = <&clock_mmss clk_camss_jpeg_jpeg_axi_clk>,
		<&clock_mmss clk_camss_jpeg_jpeg_ahb_clk>,
		<&clock_mmss clk_camss_ahb_clk>,
		<&clock_mmss clk_camss_top_ahb_clk>;
	clock-names = "core_clk", "iface_clk", "alt_iface_clk", "alt_core_clk";

	qcom,iommu-bfb-regs =  <0x2000
				0x204c
				0x2060
				0x2514
				0x2540
				0x256c
				0x20ac
				0x215c
				0x220c
				0x22bc
				0x2314
				0x2394
				0x2414
				0x2494
				0x2008
				0x200c
				0x2010
				0x2014>;

	qcom,iommu-bfb-data =  <0x3
				0x3ffff
				0x1555
				0x0
				0x4
				0x4
				0x2000
				0xe673
				0x2c00
				0xe616
				0x0
				0x0
				0x10
				0x68
				0x0
				0x0
				0x0
				0x0>;

	qcom,iommu-ctx@fda6f000 {
		compatible = "qcom,msm-smmu-v1-ctx";
		reg = <0xfda6f000 0x1000>;
		interrupts = <0 70 0>;
		qcom,iommu-ctx-sids = <3>;
		label = "jpeg_dma";
	};
};

&kgsl_iommu {
	status = "ok";
	vdd-supply = <&gdsc_oxili_cx>;
	qcom,alt-vdd-supply = <&gdsc_oxili_gx>;
	qcom,iommu-secure-id = <18>;
	clocks = <&clock_mmss clk_oxili_gfx3d_clk>,
		<&clock_mmss clk_oxilicx_ahb_clk>;
	clock-names = "core_clk", "iface_clk";

	qcom,iommu-bfb-regs =  <0x2000
				0x204c
				0x2060
				0x2514
				0x2540
				0x256c
				0x20ac
				0x215c
				0x220c
				0x22bc
				0x2314
				0x2394
				0x2414
				0x2494
				0x2008
				0x2600
				0x2604
				0x2608
				0x260c
				0x2610
				0x2614
				0x2618
				0x261c
				0x2620
				0x2624
				0x2628
				0x262c>;

	qcom,iommu-bfb-data =  <0x3
				0x3
				0x1555
				0x0
				0x8
				0x10
				0x0
				0x120
				0x0
				0x20
				0x0
				0x0
				0x1
				0x101
				0x0
				0x7
				0x4
				0x20
				0x8
				0x14
				0x0
				0x0
				0xc
				0x6c
				0x0
				0x8
				0x10>;

	qcom,iommu-ctx@fdb18000 {
		qcom,iommu-ctx-sids = <0 1>;
	};

	qcom,iommu-ctx@fdb19000 {
		qcom,iommu-ctx-sids = <>;
	};

	qcom,iommu-ctx@fdb1a000 {
		qcom,iommu-ctx-sids = <2>;
		interrupts = <0 241 0>, <0 240 0>;
		qcom,secure-context;
	};
};

&vfe_iommu {
	status = "ok";
	vdd-supply = <&gdsc_vfe>;
	qcom,needs-alt-core-clk;
	qcom,needs-alt-iface-clk;
	clocks = <&clock_mmss clk_camss_vfe_vfe_axi_clk>,
		<&clock_mmss clk_camss_vfe_vfe_ahb_clk>,
		<&clock_mmss clk_camss_ahb_clk>,
		<&clock_mmss clk_camss_top_ahb_clk>;
	clock-names = "core_clk", "iface_clk", "alt_iface_clk", "alt_core_clk";

	qcom,iommu-bfb-regs =  <0x2000
				0x204c
				0x2060
				0x2514
				0x2540
				0x256c
				0x20ac
				0x215c
				0x220c
				0x22bc
				0x2314
				0x2394
				0x2414
				0x2494
				0x2008
				0x200c
				0x2010
				0x2014>;

	qcom,iommu-bfb-data =  <0x3
				0xfffff
				0x1555
				0x0
				0x4
				0x4
				0x2400
				0x8844
				0x2400
				0x8812
				0x0
				0x0
				0x12
				0x5a
				0x0
				0x0
				0x0
				0x0>;
};

&fd_iommu {
	status = "ok";
	vdd-supply = <&gdsc_fd>;
	qcom,needs-alt-core-clk;
	qcom,needs-alt-iface-clk;
	clocks = <&clock_mmss clk_fd_axi_clk>,
		<&clock_mmss clk_fd_ahb_clk>,
		<&clock_mmss clk_fd_core_clk>,
		<&clock_mmss clk_fd_core_uar_clk>;
	clock-names = "core_clk", "iface_clk", "alt_core_clk", "alt_iface_clk";
};

&cpp_iommu {
	status = "ok";
	vdd-supply = <&gdsc_cpp>;
        qcom,needs-alt-core-clk;
        qcom,needs-alt-iface-clk;
	clocks = <&clock_mmss clk_camss_vfe_cpp_axi_clk>,
		<&clock_mmss clk_camss_vfe_cpp_ahb_clk>,
                <&clock_mmss clk_camss_ahb_clk>,
                <&clock_mmss clk_camss_top_ahb_clk>;
	clock-names = "core_clk", "iface_clk", "alt_iface_clk", "alt_core_clk";
};