/* Copyright (c) 2013 - 2014, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&soc {
	tmc_etr: tmc@826000 {
		compatible = "arm,coresight-tmc";
		reg = <0x826000 0x1000>,
		      <0x884000 0x15000>;
		reg-names = "tmc-base", "bam-base";
		interrupts = <0 166 0>;
		interrupt-names = "byte-cntr-irq";

		qcom,memory-size = <0x100000>;
		qcom,tmc-flush-powerdown;

		coresight-id = <0>;
		coresight-name = "coresight-tmc-etr";
		coresight-nr-inports = <1>;
		coresight-ctis = <&cti0 &cti8>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	tpiu: tpiu@820000 {
		compatible = "arm,coresight-tpiu";
		reg = <0x820000 0x1000>,
		      <0x1100000 0xb0000>;
		reg-names = "tpiu-base", "nidnt-base";

		coresight-id = <1>;
		coresight-name = "coresight-tpiu";
		coresight-nr-inports = <1>;

		qcom,nidnthw;
		qcom,nidnt-swduart;
		qcom,nidnt-swdtrc;
		qcom,nidnt-jtag;
		qcom,nidnt-spmi;
		nidnt-gpio = <38>;
		nidnt-gpio-polarity = <1>;

		interrupts = <0 82 0>;
		interrupt-names = "nidnt-irq";

		vdd-supply = <&pm8916_l11>;
		qcom,vdd-voltage-level = <2950000 2950000>;
		qcom,vdd-current-level = <15000 400000>;

		vdd-io-supply = <&pm8916_l12>;
		qcom,vdd-io-voltage-level = <2950000 2950000>;
		qcom,vdd-io-current-level = <200 50000>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	replicator: replicator@824000 {
		compatible = "qcom,coresight-replicator";
		reg = <0x824000 0x1000>;
		reg-names = "replicator-base";

		coresight-id = <2>;
		coresight-name = "coresight-replicator";
		coresight-nr-inports = <1>;
		coresight-outports = <0 1>;
		coresight-child-list = <&tmc_etr &tpiu>;
		coresight-child-ports = <0 0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	tmc_etf: tmc@825000 {
		compatible = "arm,coresight-tmc";
		reg = <0x825000 0x1000>;
		reg-names = "tmc-base";

		coresight-id = <3>;
		coresight-name = "coresight-tmc-etf";
		coresight-nr-inports = <1>;
		coresight-outports = <0>;
		coresight-child-list = <&replicator>;
		coresight-child-ports = <0>;
		coresight-default-sink;
		coresight-ctis = <&cti0 &cti8>;

		qcom,tmc-flush-powerdown;

		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	funnel_in0: funnel@821000 {
		compatible = "arm,coresight-funnel";
		reg = <0x821000 0x1000>;
		reg-names = "funnel-base";

		coresight-id = <4>;
		coresight-name = "coresight-funnel-in0";
		coresight-nr-inports = <8>;
		coresight-outports = <0>;
		coresight-child-list = <&tmc_etf>;
		coresight-child-ports = <0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	funnel_apss: funnel@841000 {
		compatible = "arm,coresight-funnel";
		reg = <0x841000 0x1000>;
		reg-names = "funnel-base";

		coresight-id = <5>;
		coresight-name = "coresight-funnel-apss";
		coresight-nr-inports = <4>;
		coresight-outports = <0>;
		coresight-child-list = <&funnel_in0>;
		coresight-child-ports = <4>;

		qcom,funnel-save-restore;

		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	funnel_in2: funnel@869000 {
		compatible = "arm,coresight-funnel";
		reg = <0x869000 0x1000>;
		reg-names = "funnel-base";

		coresight-id = <6>;
		coresight-name = "coresight-funnel-in2";
		coresight-nr-inports = <8>;
		coresight-outports = <0>;
		coresight-child-list = <&funnel_in0>;
		coresight-child-ports = <6>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	funnel_in3: funnel@868000 {
		compatible = "arm,coresight-funnel";
		reg = <0x868000 0x1000>;
		reg-names = "funnel-base";

		coresight-id = <7>;
		coresight-name = "coresight-funnel-in3";
		coresight-nr-inports = <2>;
		coresight-outports = <0>;
		coresight-child-list = <&funnel_in2>;
		coresight-child-ports = <7>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	stm: stm@802000 {
		compatible = "arm,coresight-stm";
		reg = <0x802000 0x1000>,
		      <0x9280000 0x180000>;
		reg-names = "stm-base", "stm-data-base";

		coresight-id = <8>;
		coresight-name = "coresight-stm";
		coresight-nr-inports = <0>;
		coresight-outports = <0>;
		coresight-child-list = <&funnel_in0>;
		coresight-child-ports = <7>;

		qcom,data-barrier;

		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	csr: csr@801000 {
		compatible = "qcom,coresight-csr";
		reg = <0x801000 0x1000>;
		reg-names = "csr-base";

		coresight-id = <9>;
		coresight-name = "coresight-csr";
		coresight-nr-inports = <0>;

		qcom,blk-size = <1>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	etm0: etm@85c000 {
		compatible = "arm,coresight-etmv4";
		reg = <0x85c000 0x1000>;
		reg-names = "etm-base";

		coresight-id = <10>;
		coresight-name = "coresight-etm0";
		coresight-nr-inports = <0>;
		coresight-outports = <0>;
		coresight-child-list = <&funnel_apss>;
		coresight-child-ports = <0>;
		coresight-etm-cpu = <&CPU0>;

		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	etm1: etm@85d000 {
		compatible = "arm,coresight-etmv4";
		reg = <0x85d000 0x1000>;
		reg-names = "etm-base";

		coresight-id = <11>;
		coresight-name = "coresight-etm1";
		coresight-nr-inports = <0>;
		coresight-outports = <0>;
		coresight-child-list = <&funnel_apss>;
		coresight-child-ports = <1>;
		coresight-etm-cpu = <&CPU1>;

		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	etm2: etm@85e000 {
		compatible = "arm,coresight-etmv4";
		reg = <0x85e000 0x1000>;
		reg-names = "etm-base";

		coresight-id = <12>;
		coresight-name = "coresight-etm2";
		coresight-nr-inports = <0>;
		coresight-outports = <0>;
		coresight-child-list = <&funnel_apss>;
		coresight-child-ports = <2>;
		coresight-etm-cpu = <&CPU2>;

		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	etm3: etm@85f000 {
		compatible = "arm,coresight-etmv4";
		reg = <0x85f000 0x1000>;
		reg-names = "etm-base";

		coresight-id = <13>;
		coresight-name = "coresight-etm3";
		coresight-nr-inports = <0>;
		coresight-outports = <0>;
		coresight-child-list = <&funnel_apss>;
		coresight-child-ports = <3>;
		coresight-etm-cpu = <&CPU3>;

		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	rpm_etm0 {
		compatible = "qcom,coresight-rpm-etm";

		coresight-id = <14>;
		coresight-name = "coresight-rpm-etm0";
		coresight-nr-inports = <0>;
		coresight-outports = <0>;
		coresight-child-list = <&funnel_in0>;
		coresight-child-ports = <0>;
	};

	wcn_etm0 {
		compatible = "qcom,coresight-wcn-etm";

		coresight-id = <15>;
		coresight-name = "coresight-wcn-etm0";
		coresight-nr-inports = <0>;
		coresight-outports = <0>;
		coresight-child-list = <&funnel_in3>;
		coresight-child-ports = <0>;
	};

	modem_etm0 {
		compatible = "qcom,coresight-modem-etm";

		coresight-id = <16>;
		coresight-name = "coresight-modem-etm0";
		coresight-nr-inports = <0>;
		coresight-outports = <0>;
		coresight-child-list = <&funnel_in0>;
		coresight-child-ports = <2>;
	};

	cti0: cti@810000 {
		compatible = "arm,coresight-cti";
		reg = <0x810000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <17>;
		coresight-name = "coresight-cti0";
		coresight-nr-inports = <0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	cti1: cti@811000 {
		compatible = "arm,coresight-cti";
		reg = <0x811000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <18>;
		coresight-name = "coresight-cti1";
		coresight-nr-inports = <0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	cti2: cti@812000 {
		compatible = "arm,coresight-cti";
		reg = <0x812000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <19>;
		coresight-name = "coresight-cti2";
		coresight-nr-inports = <0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	cti3: cti@813000 {
		compatible = "arm,coresight-cti";
		reg = <0x813000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <20>;
		coresight-name = "coresight-cti3";
		coresight-nr-inports = <0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	cti4: cti@814000 {
		compatible = "arm,coresight-cti";
		reg = <0x814000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <21>;
		coresight-name = "coresight-cti4";
		coresight-nr-inports = <0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	cti5: cti@815000 {
		compatible = "arm,coresight-cti";
		reg = <0x815000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <22>;
		coresight-name = "coresight-cti5";
		coresight-nr-inports = <0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	cti6: cti@816000 {
		compatible = "arm,coresight-cti";
		reg = <0x816000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <23>;
		coresight-name = "coresight-cti6";
		coresight-nr-inports = <0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	cti7: cti@817000 {
		compatible = "arm,coresight-cti";
		reg = <0x817000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <24>;
		coresight-name = "coresight-cti7";
		coresight-nr-inports = <0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	cti8: cti@818000 {
		compatible = "arm,coresight-cti";
		reg = <0x818000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <25>;
		coresight-name = "coresight-cti8";
		coresight-nr-inports = <0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	cti_cpu0: cti@858000 {
		compatible = "arm,coresight-cti";
		reg = <0x858000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <26>;
		coresight-name = "coresight-cti-cpu0";
		coresight-nr-inports = <0>;
		coresight-cti-cpu = <&CPU0>;

		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";

		qcom,cti-save;
	};

	cti_cpu1: cti@859000 {
		compatible = "arm,coresight-cti";
		reg = <0x859000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <27>;
		coresight-name = "coresight-cti-cpu1";
		coresight-nr-inports = <0>;
		coresight-cti-cpu = <&CPU1>;

		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";

		qcom,cti-save;
	};

	cti_cpu2: cti@85a000 {
		compatible = "arm,coresight-cti";
		reg = <0x85a000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <28>;
		coresight-name = "coresight-cti-cpu2";
		coresight-nr-inports = <0>;
		coresight-cti-cpu = <&CPU2>;

		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";

		qcom,cti-save;
	};

	cti_cpu3: cti@85b000 {
		compatible = "arm,coresight-cti";
		reg = <0x85b000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <29>;
		coresight-name = "coresight-cti-cpu3";
		coresight-nr-inports = <0>;
		coresight-cti-cpu = <&CPU3>;

		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";

		qcom,cti-save;
	};

	cti_video_cpu0: cti@830000 {
		compatible = "arm,coresight-cti";
		reg = <0x830000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <30>;
		coresight-name = "coresight-cti-video-cpu0";
		coresight-nr-inports = <0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	cti_wcn_cpu0: cti@835000 {
		compatible = "arm,coresight-cti";
		reg = <0x835000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <31>;
		coresight-name = "coresight-cti-wcn-cpu0";
		coresight-nr-inports = <0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	cti_modem_cpu0: cti@838000 {
		compatible = "arm,coresight-cti";
		reg = <0x838000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <32>;
		coresight-name = "coresight-cti-modem-cpu0";
		coresight-nr-inports = <0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	cti_rpm_cpu0: cti@83c000 {
		compatible = "arm,coresight-cti";
		reg = <0x83c000 0x1000>;
		reg-names = "cti-base";

		coresight-id = <33>;
		coresight-name = "coresight-cti-rpm-cpu0";
		coresight-nr-inports = <0>;
		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	fuse: fuse@5e01c {
		compatible = "arm,coresight-fuse-v2";
		reg = <0x5e01c 0x8>,
		      <0x58040 0x4>,
		      <0x5e00c 0x4>;
		reg-names = "fuse-base", "nidnt-fuse-base", "qpdi-fuse-base";

		coresight-id = <34>;
		coresight-name = "coresight-fuse";
		coresight-nr-inports = <0>;
	};

	hwevent: hwevent@86c000 {
		compatible = "qcom,coresight-hwevent";
		reg = <0x86c000 0x108>,
		      <0x86cfb0 0x4>,
		      <0x200c000 0x28>,
		      <0x78c5010 0x4>,
		      <0x7885010 0x4>;
		reg-names = "wrapper-mux", "wrapper-lockaccess", "spmi-mux",
		            "usbbam-mux", "blsp-mux";
		coresight-id = <35>;
		coresight-name = "coresight-hwevent";
		coresight-nr-inports = <0>;

		clocks = <&clock_rpm clk_qdss_clk>,
			 <&clock_rpm clk_qdss_a_clk>;
		clock-names = "core_clk", "core_a_clk";
	};

	qpdi: qpdi@1941000 {
		compatible = "qcom,coresight-qpdi";
		reg = <0x1941000 0x4>;
		reg-names = "qpdi-base";

		coresight-id = <36>;
		coresight-name = "coresight-qpdi";
		coresight-nr-inports = <0>;

		vdd-supply = <&pm8916_l11>;
		qcom,vdd-voltage-level = <2950000 2950000>;
		qcom,vdd-current-level = <15000 400000>;

		vdd-io-supply = <&pm8916_l12>;
		qcom,vdd-io-voltage-level = <2950000 2950000>;
		qcom,vdd-io-current-level = <200 50000>;
	};
};