/*
 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&soc {
	qcom,msm-cam@1800000{
		compatible = "qcom,msm-cam";
	};

	qcom,csiphy@1b0ac00 {
		cell-index = <0>;
		compatible = "qcom,csiphy-v3.1", "qcom,csiphy";
		reg = <0x1b0ac00 0x200>,
			<0x1b00030 0x4>;
		reg-names = "csiphy", "csiphy_clk_mux";
		interrupts = <0 78 0>;
		interrupt-names = "csiphy";
		clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
			<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
			<&clock_gcc clk_csi0phytimer_clk_src>,
			<&clock_gcc clk_gcc_camss_csi0phytimer_clk>,
			<&clock_gcc clk_camss_ahb_clk_src>,
			<&clock_gcc clk_gcc_camss_csi0phy_clk>,
			<&clock_gcc clk_gcc_camss_ahb_clk>;
		clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",
			"csiphy_timer_src_clk", "csiphy_timer_clk",
			"camss_ahb_src", "csi_phy_clk",
			"camss_ahb_clk";
		qcom,clock-rates = <0 0 200000000 0 0 0 0>;
	};

	qcom,csiphy@1b0b000 {
		cell-index = <1>;
		compatible = "qcom,csiphy-v3.1", "qcom,csiphy";
		reg = <0x1b0b000 0x200>,
			<0x1b00038 0x4>;
		reg-names = "csiphy", "csiphy_clk_mux";
		interrupts = <0 79 0>;
		interrupt-names = "csiphy";
		clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
			<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
			<&clock_gcc clk_csi1phytimer_clk_src>,
			<&clock_gcc clk_gcc_camss_csi1phytimer_clk>,
			<&clock_gcc clk_camss_ahb_clk_src>,
			<&clock_gcc clk_gcc_camss_csi1phy_clk>,
			<&clock_gcc clk_gcc_camss_ahb_clk>;
		clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",
			"csiphy_timer_src_clk", "csiphy_timer_clk",
			"camss_ahb_src", "csi_phy_clk",
			"camss_ahb_clk";
		qcom,clock-rates = <0 0 200000000 0 0 0 0>;
	};

	qcom,csid@1b08000  {
		cell-index = <0>;
		compatible = "qcom,csid-v3.1", "qcom,csid";
		reg = <0x1b08000 0x100>;
		reg-names = "csid";
		interrupts = <0 51 0>;
		interrupt-names = "csid";
		qcom,csi-vdd-voltage = <1200000>;
		qcom,mipi-csi-vdd-supply = <&pm8916_l2>;
		clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
			<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
			<&clock_gcc clk_gcc_camss_csi0_ahb_clk>,
			<&clock_gcc clk_csi0_clk_src>,
			<&clock_gcc clk_gcc_camss_csi0_clk>,
			<&clock_gcc clk_gcc_camss_csi0pix_clk>,
			<&clock_gcc clk_gcc_camss_csi0rdi_clk>,
			<&clock_gcc clk_gcc_camss_ahb_clk>;
		clock-names = "camss_top_ahb_clk",
			"ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",
			"csi_clk",  "csi_pix_clk",
			"csi_rdi_clk", "camss_ahb_clk";
		qcom,clock-rates = <0 0 0 200000000 0 0 0 0>;
     };

	qcom,csid@1b08400 {
		cell-index = <1>;
		compatible = "qcom,csid-v3.1", "qcom,csid";
		reg = <0x1b08400 0x100>;
		reg-names = "csid";
		interrupts = <0 52 0>;
		interrupt-names = "csid";
		qcom,csi-vdd-voltage = <1200000>;
		qcom,mipi-csi-vdd-supply = <&pm8916_l2>;
		clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
			<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
			<&clock_gcc clk_gcc_camss_csi1_ahb_clk>,
			<&clock_gcc clk_csi1_clk_src>,
			<&clock_gcc clk_gcc_camss_csi1_clk>,
			<&clock_gcc clk_gcc_camss_csi1pix_clk>,
			<&clock_gcc clk_gcc_camss_csi1rdi_clk>,
			<&clock_gcc clk_gcc_camss_ahb_clk>;
		clock-names = "camss_top_ahb_clk",
			"ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",
			"csi_clk", "csi_pix_clk",
			"csi_rdi_clk", "camss_ahb_clk";
		qcom,clock-rates = <0 0 0 200000000 0 0 0 0>;
	};

	qcom,ispif@1b0a000 {
		cell-index = <0>;
		compatible = "qcom,ispif-v3.0", "qcom,ispif";
		reg = <0x1b0a000 0x500>,
			<0x1b00020 0x10>;
		reg-names = "ispif", "csi_clk_mux";
		interrupts = <0 55 0>;
		interrupt-names = "ispif";
		clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
		<&clock_gcc clk_gcc_camss_ahb_clk>,
		<&clock_gcc clk_csi0_clk_src>,
		<&clock_gcc clk_gcc_camss_csi0_clk>,
		<&clock_gcc clk_gcc_camss_csi0pix_clk>,
		<&clock_gcc clk_gcc_camss_csi0rdi_clk>,
		<&clock_gcc clk_csi1_clk_src>,
		<&clock_gcc clk_gcc_camss_csi1_clk>,
		<&clock_gcc clk_gcc_camss_csi1pix_clk>,
		<&clock_gcc clk_gcc_camss_csi1rdi_clk>,
		<&clock_gcc clk_csi1_clk_src>,
		<&clock_gcc clk_gcc_camss_csi1_clk>,
		<&clock_gcc clk_gcc_camss_csi1pix_clk>,
		<&clock_gcc clk_gcc_camss_csi1rdi_clk>,
		<&clock_gcc clk_csi1_clk_src>,
		<&clock_gcc clk_gcc_camss_csi1_clk>,
		<&clock_gcc clk_gcc_camss_csi1pix_clk>,
		<&clock_gcc clk_gcc_camss_csi1rdi_clk>,
		<&clock_gcc clk_vfe0_clk_src>,
		<&clock_gcc clk_gcc_camss_vfe0_clk>,
		<&clock_gcc clk_gcc_camss_csi_vfe0_clk>,
		<&clock_gcc clk_vfe0_clk_src>,
		<&clock_gcc clk_gcc_camss_vfe0_clk>,
		<&clock_gcc clk_gcc_camss_csi_vfe0_clk>;
        clock-names = "ispif_ahb_clk","camss_ahb_clk",
            "csi0_src_clk", "csi0_clk",
            "csi0_pix_clk","csi0_rdi_clk", "csi1_src_clk",
            "csi1_clk", "csi1_pix_clk", "csi1_rdi_clk",
            "csi2_src_clk","csi2_clk", "csi2_pix_clk","csi2_rdi_clk",
            "csi3_src_clk","csi3_clk", "csi3_pix_clk",
            "csi3_rdi_clk", "vfe0_clk_src", "camss_vfe_vfe0_clk",
            "camss_csi_vfe0_clk","vfe1_clk_src","camss_vfe_vfe1_clk",
            "camss_csi_vfe1_clk";
	qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;
	};

	qcom,vfe@1b10000 {
		cell-index = <0>;
		compatible = "qcom,vfe40";
		reg = <0x1b10000 0x1000>,
			<0x1b40000 0x200>;
		reg-names = "vfe", "vfe_vbif";
		interrupts = <0 57 0>;
		interrupt-names = "vfe";
		vdd-supply = <&gdsc_vfe>;
		clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
			 <&clock_gcc clk_vfe0_clk_src>,
			 <&clock_gcc clk_gcc_camss_vfe0_clk>,
			 <&clock_gcc clk_gcc_camss_csi_vfe0_clk>,
			 <&clock_gcc clk_gcc_camss_vfe_ahb_clk>,
			 <&clock_gcc clk_gcc_camss_vfe_axi_clk>,
			 <&clock_gcc clk_gcc_camss_ahb_clk>;
		clock-names = "camss_top_ahb_clk", "vfe_clk_src",
			"camss_vfe_vfe_clk", "camss_csi_vfe_clk", "iface_clk",
			"bus_clk", "camss_ahb_clk";
		qcom,clock-rates = <0 266670000 0 0 0 0 0>;
		qos-entries = <8>;
		qos-regs = <0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8
				0x2DC 0x2E0>;
		qos-settings = <0xAAA5AAA5 0xAAA5AAA5 0xAAA5AAA5
				0xAAA5AAA5 0xAAA5AAA5 0xAAA5AAA5
				0xAAA5AAA5 0x0001AAA5>;
		};

	qcom,jpeg@1b1c000 {
		cell-index = <0>;
		compatible = "qcom,jpeg";
		reg = <0x1b1c000 0x400>,
			<0x1b60000 0xc30>;
		reg-names = "jpeg";
		interrupts = <0 59 0>;
		interrupt-names = "jpeg";
		vdd-supply = <&gdsc_jpeg>;
		clocks = <&clock_gcc clk_gcc_camss_jpeg0_clk>,
			 <&clock_gcc clk_gcc_camss_jpeg_ahb_clk>,
			 <&clock_gcc clk_gcc_camss_jpeg_axi_clk>,
			 <&clock_gcc clk_gcc_camss_top_ahb_clk>,
			 <&clock_gcc clk_gcc_camss_ahb_clk>;
		clock-names = "core_clk", "iface_clk",
			"bus_clk0", "camss_top_ahb_clk",
			"camss_ahb_clk";
		qcom,clock-rates = <266670000 0 0 0 0>;
	};

	qcom,irqrouter@1b00000 {
		cell-index = <0>;
		compatible = "qcom,irqrouter";
		reg = <0x1b00000 0x100>;
		reg-names = "irqrouter";
	};

	qcom,cpp@1b04000 {
		cell-index = <0>;
		compatible = "qcom,cpp";
		reg = <0x1b04000 0x100>,
		      <0x1b40000 0x200>,
		      <0x1b18000 0x018>;
		reg-names = "cpp", "cpp_vbif", "cpp_hw";
		interrupts = <0 49 0>;
		interrupt-names = "cpp";
		vdd-supply = <&gdsc_vfe>;
		clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
			<&clock_gcc clk_vfe0_clk_src>,
			<&clock_gcc clk_gcc_camss_vfe0_clk>,
			<&clock_gcc clk_gcc_camss_vfe_ahb_clk>,
			<&clock_gcc clk_gcc_camss_cpp_clk>,
			<&clock_gcc clk_gcc_camss_cpp_ahb_clk>,
			<&clock_gcc clk_gcc_camss_vfe_axi_clk>,
			<&clock_gcc clk_gcc_camss_micro_ahb_clk>,
			<&clock_gcc clk_gcc_camss_ahb_clk>;
		clock-names = "camss_top_ahb_clk", "vfe_clk_src",
			"camss_vfe_vfe_clk", "iface_clk", "cpp_core_clk",
			"cpp_iface_clk", "cpp_bus_clk", "micro_iface_clk",
			"camss_ahb_clk";
		qcom,clock-rates = <0 320000000 0 80000000 320000000 0 0 0 0>;
	};

	cci: qcom,cci@1b0c000 {
		cell-index = <0>;
		compatible = "qcom,cci";
		reg = <0x1b0c000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "cci";
		interrupts = <0 50 0>;
		interrupt-names = "cci";
		clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
			 <&clock_gcc clk_cci_clk_src>,
			 <&clock_gcc clk_gcc_camss_cci_ahb_clk>,
			 <&clock_gcc clk_gcc_camss_cci_clk>,
			 <&clock_gcc clk_gcc_camss_ahb_clk>;
		clock-names = "camss_top_ahb_clk", "cci_src_clk",
			"cci_ahb_clk", "cci_clk", "camss_ahb_clk";
		qcom,clock-rates = <0 19200000 80000000 0 0>,
				<0 37500000 80000000 0 0>;
		pinctrl-names = "cci_default", "cci_suspend";
		pinctrl-0 = <&cci0_default>;
		pinctrl-1 = <&cci0_sleep>;
		gpios = <&msm_gpio 29 0>,
			<&msm_gpio 30 0>;
		qcom,gpio-tbl-num = <0 1>;
		qcom,gpio-tbl-flags = <1 1>;
		qcom,gpio-tbl-label = "CCI_I2C_DATA0",
				      "CCI_I2C_CLK0";
		i2c_freq_100Khz: qcom,i2c_standard_mode {
			status = "disabled";
		};
		i2c_freq_400Khz: qcom,i2c_fast_mode {
			status = "disabled";
		};
		i2c_freq_custom: qcom,i2c_custom_mode {
			status = "disabled";
		};

		i2c_freq_1Mhz: qcom,i2c_fast_plus_mode {
			status = "disabled";
		};

	};
};

&i2c_freq_100Khz {
	qcom,hw-thigh = <78>;
	qcom,hw-tlow = <114>;
	qcom,hw-tsu-sto = <28>;
	qcom,hw-tsu-sta = <28>;
	qcom,hw-thd-dat = <10>;
	qcom,hw-thd-sta = <77>;
	qcom,hw-tbuf = <118>;
	qcom,hw-scl-stretch-en = <0>;
	qcom,hw-trdhld = <6>;
	qcom,hw-tsp = <1>;
	status = "ok";
};

&i2c_freq_400Khz {
	qcom,hw-thigh = <20>;
	qcom,hw-tlow = <28>;
	qcom,hw-tsu-sto = <21>;
	qcom,hw-tsu-sta = <21>;
	qcom,hw-thd-dat = <13>;
	qcom,hw-thd-sta = <18>;
	qcom,hw-tbuf = <32>;
	qcom,hw-scl-stretch-en = <0>;
	qcom,hw-trdhld = <6>;
	qcom,hw-tsp = <3>;
	status = "ok";
};

&i2c_freq_custom {
	qcom,hw-thigh = <15>;
	qcom,hw-tlow = <28>;
	qcom,hw-tsu-sto = <21>;
	qcom,hw-tsu-sta = <21>;
	qcom,hw-thd-dat = <13>;
	qcom,hw-thd-sta = <18>;
	qcom,hw-tbuf = <25>;
	qcom,hw-scl-stretch-en = <1>;
	qcom,hw-trdhld = <6>;
	qcom,hw-tsp = <3>;
	status = "ok";
};

&i2c_freq_1Mhz {
	qcom,hw-thigh = <16>;
	qcom,hw-tlow = <22>;
	qcom,hw-tsu-sto = <17>;
	qcom,hw-tsu-sta = <18>;
	qcom,hw-thd-dat = <16>;
	qcom,hw-thd-sta = <15>;
	qcom,hw-tbuf = <19>;
	qcom,hw-scl-stretch-en = <1>;
	qcom,hw-trdhld = <3>;
	qcom,hw-tsp = <3>;
	qcom,cci-clk-src = <37500000>;
	status = "ok";
};