diff options
author | Larry Bassel <lbassel@codeaurora.org> | 2014-01-17 10:33:08 -0800 |
---|---|---|
committer | Georgi Djakov <georgi.djakov@linaro.org> | 2015-02-19 10:50:53 +0200 |
commit | 4b28aed9cf9ac14d3f0e0432abbe85e612f0814b (patch) | |
tree | fb7f8a66de5582a7a33e3dd3a4f31d7733735c67 /arch/arm64/mm/cache.S | |
parent | ac87347290b1d866c238320be1c838b20b263f09 (diff) |
arm64: provide dma cache routines with same API as 32 bit
The APIs __dma_inv_range() and __dma_clean_range() were
not exported by the third party patch. Since the functions
starting with underscores are not to be directly used by drivers,
related functions without the underscores are provided
which have the same name and functionality as the 32 bit APIs.
Change-Id: Ie0e681614307d9d9a19e58cacfb9b5dff4528977
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>
arm64: add defines for dmac_*_range for compatibility with arm32
An earlier patch created defines for dma_*_range APIs to be
compatible with arm 32 bit, however it appears
these API names have not (at least yet) appeared there, so
revise the names to dmac_*_range, which is defined
for arm 32 bit so that there is one name defined
for both architectures.
Change-Id: I6456c02bad73fb54a874dc9925d3d43d9b8be2f2
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Diffstat (limited to 'arch/arm64/mm/cache.S')
-rw-r--r-- | arch/arm64/mm/cache.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 2560e1e1562..2662ffa3dba 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -186,7 +186,7 @@ ENTRY(__inval_cache_range) * - start - virtual start address of region * - end - virtual end address of region */ -__dma_inv_range: +ENTRY(__dma_inv_range) dcache_line_size x2, x3 sub x3, x2, #1 tst x1, x3 // end cache line aligned? @@ -212,7 +212,7 @@ ENDPROC(__dma_inv_range) * - start - virtual start address of region * - end - virtual end address of region */ -__dma_clean_range: +ENTRY(__dma_clean_range) dcache_line_size x2, x3 sub x3, x2, #1 bic x0, x0, x3 |