From 0174fc04fdfd7a84c2655d84aa704fe173798241 Mon Sep 17 00:00:00 2001 From: Chunsang Jeong Date: Mon, 26 Sep 2011 11:19:39 -0600 Subject: Added Mali, UMP and Mali DRM kernel driver Conflicts: drivers/gpu/drm/Kconfig drivers/gpu/drm/Makefile Signed-off-by: Chunsang Jeong Signed-off-by: Tushar Behera --- drivers/gpu/arm/mali/regs/mali_200_regs.h | 170 ++++++++++++++++++++++++++++++ 1 file changed, 170 insertions(+) create mode 100644 drivers/gpu/arm/mali/regs/mali_200_regs.h (limited to 'drivers/gpu/arm/mali/regs/mali_200_regs.h') diff --git a/drivers/gpu/arm/mali/regs/mali_200_regs.h b/drivers/gpu/arm/mali/regs/mali_200_regs.h new file mode 100644 index 00000000000..e9da7ab8110 --- /dev/null +++ b/drivers/gpu/arm/mali/regs/mali_200_regs.h @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2010 ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence. + * + * A copy of the licence is included with the program, and can also be obtained from Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _MALI200_REGS_H_ +#define _MALI200_REGS_H_ + +/** + * Enum for management register addresses. + */ +enum mali200_mgmt_reg +{ + MALI200_REG_ADDR_MGMT_VERSION = 0x1000, + MALI200_REG_ADDR_MGMT_CURRENT_REND_LIST_ADDR = 0x1004, + MALI200_REG_ADDR_MGMT_STATUS = 0x1008, + MALI200_REG_ADDR_MGMT_CTRL_MGMT = 0x100c, + + MALI200_REG_ADDR_MGMT_INT_RAWSTAT = 0x1020, + MALI200_REG_ADDR_MGMT_INT_CLEAR = 0x1024, + MALI200_REG_ADDR_MGMT_INT_MASK = 0x1028, + MALI200_REG_ADDR_MGMT_INT_STATUS = 0x102c, + + MALI200_REG_ADDR_MGMT_WRITE_BOUNDARY_LOW = 0x1044, + + MALI200_REG_ADDR_MGMT_BUS_ERROR_STATUS = 0x1050, + + MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE = 0x1080, + MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC = 0x1084, + MALI200_REG_ADDR_MGMT_PERF_CNT_0_VALUE = 0x108c, + + MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE = 0x10a0, + MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC = 0x10a4, + MALI200_REG_ADDR_MGMT_PERF_CNT_1_VALUE = 0x10ac, + + MALI200_REG_SIZEOF_REGISTER_BANK = 0x10f0 + +}; + +#define MALI200_REG_VAL_PERF_CNT_ENABLE 1 + +enum mali200_mgmt_ctrl_mgmt { + MALI200_REG_VAL_CTRL_MGMT_STOP_BUS = (1<<0), +#if defined(USING_MALI200) + MALI200_REG_VAL_CTRL_MGMT_FLUSH_CACHES = (1<<3), +#endif + MALI200_REG_VAL_CTRL_MGMT_FORCE_RESET = (1<<5), + MALI200_REG_VAL_CTRL_MGMT_START_RENDERING = (1<<6), +#if defined(USING_MALI400) + MALI400PP_REG_VAL_CTRL_MGMT_SOFT_RESET = (1<<7), +#endif +}; + +enum mali200_mgmt_irq { + MALI200_REG_VAL_IRQ_END_OF_FRAME = (1<<0), + MALI200_REG_VAL_IRQ_END_OF_TILE = (1<<1), + MALI200_REG_VAL_IRQ_HANG = (1<<2), + MALI200_REG_VAL_IRQ_FORCE_HANG = (1<<3), + MALI200_REG_VAL_IRQ_BUS_ERROR = (1<<4), + MALI200_REG_VAL_IRQ_BUS_STOP = (1<<5), + MALI200_REG_VAL_IRQ_CNT_0_LIMIT = (1<<6), + MALI200_REG_VAL_IRQ_CNT_1_LIMIT = (1<<7), + MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR = (1<<8), + MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND = (1<<9), + MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW = (1<<10), + MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW = (1<<11), + MALI400PP_REG_VAL_IRQ_RESET_COMPLETED = (1<<12), +}; + +#if defined USING_MALI200 +#define MALI200_REG_VAL_IRQ_MASK_ALL ((enum mali200_mgmt_irq) (\ + MALI200_REG_VAL_IRQ_END_OF_FRAME |\ + MALI200_REG_VAL_IRQ_END_OF_TILE |\ + MALI200_REG_VAL_IRQ_HANG |\ + MALI200_REG_VAL_IRQ_FORCE_HANG |\ + MALI200_REG_VAL_IRQ_BUS_ERROR |\ + MALI200_REG_VAL_IRQ_BUS_STOP |\ + MALI200_REG_VAL_IRQ_CNT_0_LIMIT |\ + MALI200_REG_VAL_IRQ_CNT_1_LIMIT |\ + MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR)) +#elif defined USING_MALI400 +#define MALI200_REG_VAL_IRQ_MASK_ALL ((enum mali200_mgmt_irq) (\ + MALI200_REG_VAL_IRQ_END_OF_FRAME |\ + MALI200_REG_VAL_IRQ_END_OF_TILE |\ + MALI200_REG_VAL_IRQ_HANG |\ + MALI200_REG_VAL_IRQ_FORCE_HANG |\ + MALI200_REG_VAL_IRQ_BUS_ERROR |\ + MALI200_REG_VAL_IRQ_BUS_STOP |\ + MALI200_REG_VAL_IRQ_CNT_0_LIMIT |\ + MALI200_REG_VAL_IRQ_CNT_1_LIMIT |\ + MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR |\ + MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND |\ + MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW |\ + MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW |\ + MALI400PP_REG_VAL_IRQ_RESET_COMPLETED)) +#else +#error "No supported mali core defined" +#endif + +#if defined USING_MALI200 +#define MALI200_REG_VAL_IRQ_MASK_USED ((enum mali200_mgmt_irq) (\ + MALI200_REG_VAL_IRQ_END_OF_FRAME |\ + MALI200_REG_VAL_IRQ_HANG |\ + MALI200_REG_VAL_IRQ_FORCE_HANG |\ + MALI200_REG_VAL_IRQ_BUS_ERROR |\ + MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR)) +#elif defined USING_MALI400 +#define MALI200_REG_VAL_IRQ_MASK_USED ((enum mali200_mgmt_irq) (\ + MALI200_REG_VAL_IRQ_END_OF_FRAME |\ + MALI200_REG_VAL_IRQ_HANG |\ + MALI200_REG_VAL_IRQ_FORCE_HANG |\ + MALI200_REG_VAL_IRQ_BUS_ERROR |\ + MALI200_REG_VAL_IRQ_BUS_STOP |\ + MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR |\ + MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND |\ + MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW |\ + MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW)) +#else +#error "No supported mali core defined" +#endif + +#define MALI200_REG_VAL_IRQ_MASK_NONE ((enum mali200_mgmt_irq)(0)) + +enum mali200_mgmt_status { + MALI200_REG_VAL_STATUS_RENDERING_ACTIVE = (1<<0), + MALI200_REG_VAL_STATUS_BUS_STOPPED = (1<<4), +}; + +enum mali200_render_unit +{ + MALI200_REG_ADDR_FRAME = 0x0000, +}; + +#if defined USING_MALI200 +#define MALI200_NUM_REGS_FRAME ((0x04C/4)+1) +#elif defined USING_MALI400 +#define MALI200_NUM_REGS_FRAME ((0x058/4)+1) +#else +#error "No supported mali core defined" +#endif + +enum mali200_wb_unit { + MALI200_REG_ADDR_WB0 = 0x0100, + MALI200_REG_ADDR_WB1 = 0x0200, + MALI200_REG_ADDR_WB2 = 0x0300 +}; + +/** The number of registers in one single writeback unit */ +#ifndef MALI200_NUM_REGS_WBx +#define MALI200_NUM_REGS_WBx ((0x02C/4)+1) +#endif + +/* This should be in the top 16 bit of the version register of Mali PP */ +#if defined USING_MALI200 +#define MALI_PP_PRODUCT_ID 0xC807 +#elif defined USING_MALI400 +#define MALI300_PP_PRODUCT_ID 0xCE07 +#define MALI400_PP_PRODUCT_ID 0xCD07 +#define MALI_PP_PRODUCT_ID MALI400_PP_PRODUCT_ID +#else +#error "No supported mali core defined" +#endif + + +#endif /* _MALI200_REGS_H_ */ -- cgit v1.2.3 From 23581e6776a5df8b7971670b8324fd42c77f332a Mon Sep 17 00:00:00 2001 From: Chunsang Jeong Date: Mon, 26 Sep 2011 11:19:41 -0600 Subject: Updated Mali and UMP driver with r2p1-05rel1 released at 1st Apr from ARM. Signed-off-by: Chunsang Jeong --- drivers/gpu/arm/mali/regs/mali_200_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) mode change 100644 => 100755 drivers/gpu/arm/mali/regs/mali_200_regs.h (limited to 'drivers/gpu/arm/mali/regs/mali_200_regs.h') diff --git a/drivers/gpu/arm/mali/regs/mali_200_regs.h b/drivers/gpu/arm/mali/regs/mali_200_regs.h old mode 100644 new mode 100755 index e9da7ab8110..6b30802bb2d --- a/drivers/gpu/arm/mali/regs/mali_200_regs.h +++ b/drivers/gpu/arm/mali/regs/mali_200_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 ARM Limited. All rights reserved. + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the GNU General Public License version 2 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence. -- cgit v1.2.3 From 31dd0f8af8458680e58b4269f10c7ce027d4946b Mon Sep 17 00:00:00 2001 From: Chunsang Jeong Date: Wed, 21 Dec 2011 16:04:01 -0700 Subject: Updated Mali kernel driver with r2p3-01rel, used for Android ICS Signed-off-by: Chunsang Jeong --- drivers/gpu/arm/mali/regs/mali_200_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) mode change 100755 => 100644 drivers/gpu/arm/mali/regs/mali_200_regs.h (limited to 'drivers/gpu/arm/mali/regs/mali_200_regs.h') diff --git a/drivers/gpu/arm/mali/regs/mali_200_regs.h b/drivers/gpu/arm/mali/regs/mali_200_regs.h old mode 100755 new mode 100644 index 6b30802bb2d..e9da7ab8110 --- a/drivers/gpu/arm/mali/regs/mali_200_regs.h +++ b/drivers/gpu/arm/mali/regs/mali_200_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * Copyright (C) 2010 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the GNU General Public License version 2 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence. -- cgit v1.2.3 From 4b9c7882550e4e1e3461430c70abb652c8c1fa20 Mon Sep 17 00:00:00 2001 From: Chunsang Jeong Date: Thu, 29 Mar 2012 14:48:20 +0900 Subject: Updates r2p4-02rel, which was released Mar. 2nd at malideveloper.com Signed-off-by: Chunsang Jeong --- drivers/gpu/arm/mali/regs/mali_200_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/arm/mali/regs/mali_200_regs.h') diff --git a/drivers/gpu/arm/mali/regs/mali_200_regs.h b/drivers/gpu/arm/mali/regs/mali_200_regs.h index e9da7ab8110..36981043266 100644 --- a/drivers/gpu/arm/mali/regs/mali_200_regs.h +++ b/drivers/gpu/arm/mali/regs/mali_200_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 ARM Limited. All rights reserved. + * Copyright (C) 2010, 2012 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the GNU General Public License version 2 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence. -- cgit v1.2.3