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authorHaojian Zhuang <haojian.zhuang@gmail.com>2010-09-08 09:42:39 -0400
committerEric Miao <eric.y.miao@gmail.com>2010-09-25 09:47:04 +0800
commit07a5d146c80b7caa9e754b51f64d3fcbbc74e9c0 (patch)
treec55095cdb8a1d846c85c55a74dbde535b7d5ccc6 /drivers
parentcfc6a554d7a364997a43964b4b1290487f890447 (diff)
ARM: pxa168fb: clear enable bit when not active
While fb isn't active, we should clear CFG_GRA_ENA bit. The existing code can't clear this bit. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/video/pxa168fb.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/video/pxa168fb.c b/drivers/video/pxa168fb.c
index 5d786bd3e30..a31a77ff6f3 100644
--- a/drivers/video/pxa168fb.c
+++ b/drivers/video/pxa168fb.c
@@ -298,8 +298,8 @@ static void set_dma_control0(struct pxa168fb_info *fbi)
* Set bit to enable graphics DMA.
*/
x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);
- x |= fbi->active ? 0x00000100 : 0;
- fbi->active = 0;
+ x &= ~CFG_GRA_ENA_MASK;
+ x |= fbi->active ? CFG_GRA_ENA(1) : CFG_GRA_ENA(0);
/*
* If we are in a pseudo-color mode, we need to enable