diff options
| author | Rob Herring <rob.herring@calxeda.com> | 2012-04-28 17:12:56 -0500 |
|---|---|---|
| committer | John Rigby <john.rigby@linaro.org> | 2012-06-21 05:14:27 -0600 |
| commit | bc316ce0fac5cee0ce5e6c2cec0119aa4a76fa46 (patch) | |
| tree | ceb1bef1f9d8be2b48ca954364b90a64670ab8cc | |
| parent | b2b5abf198c8c444cdb2018d4efe57f020d84fc0 (diff) | |
UBUNTU: SAUCE: net: calxedaxgmac: fix net timeout recovery
BugLink: http://bugs.launchpad.net/bugs/1000831
Fix net tx watchdog timeout recovery. The descriptor ring was reset,
but the DMA engine was not reset to the beginning of the ring.
Also, set the number of AXI outstanding transactions to 8.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Ike Panhc <ike.pan@canonical.com>
Signed-off-by: Tim Gardner <tim.gardner@canonical.com>
| -rw-r--r-- | drivers/net/ethernet/calxeda/xgmac.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/net/ethernet/calxeda/xgmac.c b/drivers/net/ethernet/calxeda/xgmac.c index 11f667f6131..8fc5fd0fb76 100644 --- a/drivers/net/ethernet/calxeda/xgmac.c +++ b/drivers/net/ethernet/calxeda/xgmac.c @@ -210,7 +210,7 @@ #define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */ #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \ - DMA_INTR_ENA_TUE) + DMA_INTR_ENA_TUE | DMA_INTR_ENA_TIE) #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \ DMA_INTR_ENA_RWE | DMA_INTR_ENA_RSE | \ @@ -933,6 +933,7 @@ static void xgmac_tx_err(struct xgmac_priv *priv) desc_init_tx_desc(priv->dma_tx, DMA_TX_RING_SZ); priv->tx_tail = 0; priv->tx_head = 0; + writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR); writel(reg | DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL); writel(DMA_STATUS_TU | DMA_STATUS_TPS | DMA_STATUS_NIS | DMA_STATUS_AIS, @@ -972,7 +973,7 @@ static int xgmac_hw_init(struct net_device *dev) writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA); /* XGMAC requires AXI bus init. This is a 'magic number' for now */ - writel(0x000100E, ioaddr + XGMAC_DMA_AXI_BUS); + writel(0x0077000E, ioaddr + XGMAC_DMA_AXI_BUS); ctrl |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_JE | XGMAC_CONTROL_ACS | XGMAC_CONTROL_CAR; |