From 3784bf0c54114e6d47bdc46178938dd280f39492 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 7 Nov 2011 17:43:40 -0600 Subject: ARM: use cache type functions for arch_get_unmapped_area There are already cache type decoding functions, so use those instead of custom decode code which only works for ARMv6. This change also correctly enables cache colour alignment on Cortex-A9 whose I-cache is aliasing VIPT. Signed-off-by: Rob Herring Acked-by: Nicolas Pitre Signed-off-by: Nicolas Pitre --- arch/arm/mm/mmap.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c index 74be05f3e03..80e70efa318 100644 --- a/arch/arm/mm/mmap.c +++ b/arch/arm/mm/mmap.c @@ -9,8 +9,7 @@ #include #include #include -#include -#include +#include #define COLOUR_ALIGN(addr,pgoff) \ ((((addr)+SHMLBA-1)&~(SHMLBA-1)) + \ @@ -32,25 +31,15 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, struct mm_struct *mm = current->mm; struct vm_area_struct *vma; unsigned long start_addr; -#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) - unsigned int cache_type; - int do_align = 0, aliasing = 0; + int do_align = 0; + int aliasing = cache_is_vipt_aliasing() || icache_is_vipt_aliasing(); /* * We only need to do colour alignment if either the I or D - * caches alias. This is indicated by bits 9 and 21 of the - * cache type register. + * caches alias. */ - cache_type = read_cpuid_cachetype(); - if (cache_type != read_cpuid_id()) { - aliasing = (cache_type | cache_type >> 12) & (1 << 11); - if (aliasing) - do_align = filp || flags & MAP_SHARED; - } -#else -#define do_align 0 -#define aliasing 0 -#endif + if (aliasing) + do_align = filp || (flags & MAP_SHARED); /* * We enforce the MAP_FIXED case. -- cgit v1.2.3