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2011-11-16LINARO: SAUCE: work around a cross toolchain build issueJohn Rigby
Signed-off-by: John Rigby <john.rigby@linaro.org> Conflicts: arch/arm/boot/compressed/Makefile
2011-11-16LINARO: SAUCE: ASoC: omap: convert per-board modules to platform driversMans Rullgard
This converts the per-board modules to platform drivers for a device created by in main platform setup. These drivers call snd_soc_register_card() directly instead of going via a "soc-audio" device and the corresponding driver in soc-core. Signed-off-by: Mans Rullgard <mans.rullgard@linaro.org>
2011-11-16Revert "UBUNTU: SAUCE: ARM: OMAP: Add macros for comparing silicon revision"Leann Ogasawara
This reverts commit 55d03f400148ef63e9cb73232fc2a261dca27e6f. Signed-off-by: Leann Ogasawara <leann.ogasawara@canonical.com>
2011-11-16UBUNTU: SAUCE: omap3: beagle: if rev unknown, assume xM revision CRobert Nelson
BugLink: http://bugs.launchpad.net/bugs/770679 Signed-off-by: Robert Nelson <robertcnelson@gmail.com> Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com> Acked-by: Leann Ogasawara <leann.ogasawara@canonical.com> Signed-off-by: Tim Gardner <tim.gardner@canonical.com>
2011-11-16UBUNTU: SAUCE: omap3: beagle: detect new xM revision BRobert Nelson
The xM B uses a DM3730 ES1.1 over the ES1.0 on xM A's, no other board changes. BugLink: http://bugs.launchpad.net/bugs/770679 Signed-off-by: Robert Nelson <robertcnelson@gmail.com> Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com> Acked-by: Leann Ogasawara <leann.ogasawara@canonical.com> Signed-off-by: Tim Gardner <tim.gardner@canonical.com>
2011-11-16UBUNTU: SAUCE: [arm] fixup __aeabi_uldivmod undefined build errorLeann Ogasawara
When building on arm we run into the following build error due to gcc-4.6 optimizing do_div into a uldivmod call: ERROR: "__aeabi_uldivmod" [drivers/scsi/megaraid/megaraid_sas.ko] undefined! Inline some assembly to prevent the compiler optimization. Signed-off-by: Leann Ogasawara <leann.ogasawara@canonical.com>
2011-11-16UBUNTU: SAUCE: omap3: beaglexm: fix DVI initializationRicardo Salveti de Araujo
Function beagle_twl_gpio_setup is called after beagle_display_init, what makes lets reset_gpio with an invalid value at the time it request the gpio. As a side effect the DVI reset GPIO is not properly set. Also removing old code that power down DVI in a hardcoded way, as it's not necessary anymore. Tested with Beagle-xM and C4. Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com> Signed-off-by: Tim Gardner <tim.gardner@canonical.com>
2011-11-16UBUNTU: SAUCE: ARM: OMAP: Add macros for comparing silicon revisionLee Jones
BugLink: http://bugs.launchpad.net/bugs/608095 Adapted from arago project patch by Sanjeev Premi <premi@ti.com> This helps provide the required setup to enable USB Ethernet (usb0) and USB host on the XM Beagleboard (A rev). This will be submitted upstream by Steve Sakoman. Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Lee Jones <lee.jones@canonical.com> Signed-off-by: Leann Ogasawara <leann.ogasawara@canonical.com>
2011-11-16UBUNTU: ARM: Adding regulator supply for vdds_sdi.Mathieu J. Poirier
The omapfb driver couldn't locate its display sink because of an initialisation error in the DSS subsystem. This error was caused by a missing 'sdi' entry in the board power regulator list. BugLink: https://bugs.launchpad.net/bugs/597904 Signed-off-by: Mathieu Poirier <mathieu.poirier@canonical.com> Signed-off-by: Leann Ogasawara <leann.ogasawara@canonical.com>
2011-11-16UBUNTU: (no-up) arm -- enable ubuntu/ directoryEric Miao
Signed-off-by: Eric Miao <eric.miao@canonical.com> Signed-off-by: Andy Whitcroft <apw@canonical.com>
2011-11-14ARM: topdown mmap supportRob Herring
Similar to other architectures, this adds topdown mmap support in user process address space allocation policy. This allows mmap sizes greater than 2GB. This support is largely copied from MIPS and the generic implementations. The address space randomization is moved into arch_pick_mmap_layout. Tested on V-Express with ubuntu and a mmap test from here: https://bugs.launchpad.net/bugs/861296 Signed-off-by: Rob Herring <rob.herring@calxeda.com> [ The fact that the randomization is moved to arch_pick_mmap_layout is greatly weakening its effectiveness. I'm merging this patch regardless in order to give the actual fix (allow >2GB mmap) more exposure in the mean time. --np ] Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-11-14ARM: use cache type functions for arch_get_unmapped_areaRob Herring
There are already cache type decoding functions, so use those instead of custom decode code which only works for ARMv6. This change also correctly enables cache colour alignment on Cortex-A9 whose I-cache is aliasing VIPT. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-11-14ARM: cpu topology: Add debugfs interface for cpu_powerVincent Guittot
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
2011-11-14ARM: cpu topology: Add asym topology flag for using cpu0 1stVincent Guittot
Modify the CPU sched_domain flags in powersave mode for using the cpu0 in ched_mc powersave mode Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
2011-11-14ARM: cpu topology: Modify cpu_power according to cpufreqVincent Guittot
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
2011-11-14ARM: cpu topology: Modify cpu_power according to sched_mc levelVincent Guittot
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
2011-11-14ARM: scheduler: add a cpu_power functionVincent Guittot
Add an architecture specific function for setting cpu_power Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
2011-11-14ARM: cpu topology: modify cpu topologyVincent Guittot
Modify the CPU topology policy according to the sched_mc level and the cortex family Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
2011-11-14ARM: cpu topology: Add update_cpu_topology functionVincent Guittot
arch_update_cpu_topology function is called by the scheduler before building its sched_domain hierarchy. Prepare the update of the cpu topology masks in this function in addition to set it in the the store_cpu_topology which is executed only once per cpu. Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
2011-11-14ARM: cpu topology: fix warningVincent Guittot
kernel/sched.c:7354:2: warning: initialization from incompatible pointer type Align cpu_coregroup_mask prototype interface with sched_domain_mask_f typedef use int cpu instead of unsigned int cpu Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
2011-11-11Merge commit 'v3.1.1' into linaro-3.1Nicolas Pitre
2011-11-11Merge branch 'samsung_cpuidle_l2_retention' of ↵Nicolas Pitre
git://git.linaro.org/people/amitdanielk/linux into linaro-3.1
2011-11-11ARM: mach-ux500: unlock I&D l2x0 caches before initLinus Walleij
commit 1bf6d2c1bb23533af6930581cc39b74685bc29de upstream. Apparently U8500 U-Boot versions may leave the l2x0 locked down before executing the kernel. Make sure we unlock it before we initialize the l2x0. This fixes a performance problem reported by Jan Rinze. The l2x0 core has been modified to unlock the l2x0 by default, but it will not touch the locking registers if the l2x0 was already enabled, as on the ux500, so we need this quirk to make sure it is properly turned off. Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Adrian Bunk <adrian.bunk@movial.com> Reported-by: Jan Rinze <janrinze@gmail.com> Tested-by: Robert Marklund <robert.marklund@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-11-11ARM: pxa/cm-x300: properly set bt_reset pinAxel Lin
commit 1a64200ec5e93be03e27c3b2fc332e04ae443eb2 upstream. Fix below build warning and properly set bt_reset pin. CC arch/arm/mach-pxa/cm-x300.o arch/arm/mach-pxa/cm-x300.c: In function 'cm_x300_init_wi2wi': arch/arm/mach-pxa/cm-x300.c:779: warning: unused variable 'wlan_en' arch/arm/mach-pxa/cm-x300.c:795: warning: 'bt_reset' may be used uninitialized in this function Signed-off-by: Axel Lin <axel.lin@gmail.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-11-11plat-mxc: iomux-v3.h: implicitly enable pull-up/down when that's desiredPaul Fertser
commit 6571534b600b8ca1936ff5630b9e0947f21faf16 upstream. To configure pads during the initialisation a set of special constants is used, e.g. #define MX25_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP) The problem is that no pull-up/down is getting activated unless both PAD_CTL_PUE (pull-up enable) and PAD_CTL_PKE (pull/keeper module enable) set. This is clearly stated in the i.MX25 datasheet and is confirmed by the measurements on hardware. This leads to some rather hard to understand bugs such as misdetecting an absent ethernet PHY (a real bug i had), unstable data transfer etc. This might affect mx25, mx35, mx50, mx51 and mx53 SoCs. It's reasonable to expect that if the pullup value is specified, the intention was to have it actually active, so we implicitly add the needed bits. Signed-off-by: Paul Fertser <fercerpav@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-11-11ARM: smp: fix clipping of number of CPUsRussell King
commit a06f916b7a9b57447ceb875eb0a89f1a66b31bca upstream. Rather than clipping the number of CPUs using the compile-time NR_CPUS constant, use the runtime nr_cpu_ids value instead. This allows the nr_cpus command line option to work as expected. Reported-by: Mark Salter <msalter@redhat.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-11-11ARM: EXYNOS4: Added function to read chip idAmit Daniel Kachhap
This adds a function to get the revision id. This is a temporary workaround patch and may get dropped later. Signed-off-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@linaro.org>
2011-11-11ARM: exynos4: remove useless code to save/restore L2 and GIC stateAmit Daniel Kachhap
Following the merge of CPU PM notifiers and L2 resume code, this patch removes useless code to save and restore L2 and GIC registers. This is now automatically covered by suspend calls which integrated CPU PM notifiers and new sleep code that allows to resume L2 before MMU is turned on. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@linaro.org>
2011-11-11ARM: exynos4: add L2 early resume codeAmit Daniel Kachhap
This patch adds code to save L2 register configuration at boot, and to resume L2 before MMU is enabled in suspend and cpuidle resume paths. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@linaro.org>
2011-11-11ARM: exynos4: remove useless churn in sleep.SLorenzo Pieralisi
This patch cleans up sleep code in preparation for L2 resume code and hotplug functions Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2011-11-11ARM: exynos4: Add support for AFTR mode cpuidle stateAmit Daniel Kachhap
This patch adds support for AFTR(ARM OFF TOP RUNNING) mode in cpuidle driver for EXYNOS4210. L2 cache keeps their data in this mode. This patch ports the code to the latest interfaces to save/restore CPU state inclusive of CPU PM notifiers, l2 resume and cpu_suspend/resume. Signed-off-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@linaro.org>
2011-11-11ARM: 7100/1: smp_scu: remove __init annotation from scu_enable()Shawn Guo
When Cortex-A9 MPCore resumes from Dormant or Shutdown modes, SCU needs to be re-enabled. This patch removes __init annotation from function scu_enable(), so that platform resume procedure can call it to re-enable SCU. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-11-11ARM: 7114/1: cache-l2x0: add resume entry for l2 in secure modeBarry Song
we save the l2x0 registers at the first initialization, and platform codes can get them to restore l2x0 status after wakeup. Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-11-11ARM: 7090/1: CACHE-L2X0: filter start address can be 0 and is often 0Barry Song
this patch fixes the error in Rob Herring's ARM: 7009/1: l2x0: Add OF based initialization http://www.spinics.net/lists/arm-kernel/msg131123.html it has been in rmk/for-next with commit 41c86ff5b Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Rob Herring <robherring2@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-11-11ARM: 7089/1: L2X0: add explicit cpu_relax() for busy wait loopBarry Song
using cpu_relax in busy loops is a well-known idiom in the kernel. It's more for documentation purposes than technically needed here. Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-11-11ARM: 7009/1: l2x0: Add OF based initializationRob Herring
This adds probing for ARM L2x0 cache controllers via device tree. Support includes the L210, L220, and PL310 controllers. The binding allows setting up cache RAM latencies and filter addresses (PL310 only). Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Barry Song <21cnbao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-11-10ARM: LPAE: Add the Kconfig entriesCatalin Marinas
This patch adds the ARM_LPAE and ARCH_PHYS_ADDR_T_64BIT Kconfig entries allowing LPAE support to be compiled into the kernel. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-11-10ARM: LPAE: mark memory banks with start > ULONG_MAX as highmemWill Deacon
Memory banks living outside of the 32-bit physical address space do not have a 1:1 pa <-> va mapping and therefore the __va macro may wrap. This patch ensures that such banks are marked as highmem so that the Kernel doesn't try to split them up when it sees that the wrapped virtual address overlaps the vmalloc space. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-11-10ARM: LPAE: Add identity mapping support for the 3-level page table formatCatalin Marinas
With LPAE, the pgd is a separate page table with entries pointing to the pmd. The identity_mapping_add() function needs to ensure that the pgd is populated before populating the pmd level. The do..while blocks now loop over the pmd in order to have the same implementation for the two page table formats. The pmd_addr_end() definition has been removed and the generic one used instead. The pmd clean-up is done in the pgd_free() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-11-10ARM: LPAE: Add context switching supportCatalin Marinas
With LPAE, TTBRx registers are 64-bit. The ASID is stored in TTBR0 rather than a separate Context ID register. This patch makes the necessary changes to handle context switching on LPAE. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-11-10ARM: LPAE: Add fault handling supportCatalin Marinas
The DFSR and IFSR register format is different when LPAE is enabled. In addition, DFSR and IFSR have similar definitions for the fault type. This modifies the fault code to correctly handle the new format. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-11-10ARM: LPAE: Invalidate the TLB before freeing the PMDCatalin Marinas
Similar to the PTE freeing, this patch introduced __pmd_free_tlb() which invalidates the TLB before freeing a PMD page. This is needed because on newer processors the entry in the upper page table may be cached by the TLB and point to random data after the PMD has been freed. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-11-10ARM: LPAE: MMU setup for the 3-level page table formatCatalin Marinas
This patch adds the MMU initialisation for the LPAE page table format. The swapper_pg_dir size with LPAE is 5 rather than 4 pages. A new proc-v7-3level.S file contains the TTB initialisation, context switch and PTE setting code with the LPAE. The TTBRx split is based on the PAGE_OFFSET with TTBR1 used for the kernel mappings. The 36-bit mappings (supersections) and a few other memory types in mmu.c are conditionally compiled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> [ nico: fixed the ALT_SMP/ALT_UP pairing ]
2011-11-10ARM: LPAE: Page table maintenance for the 3-level formatCatalin Marinas
This patch modifies the pgd/pmd/pte manipulation functions to support the 3-level page table format. Since there is no need for an 'ext' argument to cpu_set_pte_ext(), this patch conditionally defines a different prototype for this function when CONFIG_ARM_LPAE. The patch also introduces the L_PGD_SWAPPER flag to mark pgd entries pointing to pmd tables pre-allocated in the swapper_pg_dir and avoid trying to free them at run-time. This flag is 0 with the classic page table format. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-11-10ARM: LPAE: Introduce the 3-level page table format definitionsCatalin Marinas
This patch introduces the pgtable-3level*.h files with definitions specific to the LPAE page table format (3 levels of page tables). Each table is 4KB and has 512 64-bit entries. An entry can point to a 40-bit physical address. The young, write and exec software bits share the corresponding hardware bits (negated). Other software bits use spare bits in the PTE. The patch also changes some variable types from unsigned long or int to pteval_t or pgprot_t. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-11-10ARM: LPAE: add ISBs around MMU enabling codeWill Deacon
Before we enable the MMU, we must ensure that the TTBR registers contain sane values. After the MMU has been enabled, we jump to the *virtual* address of the following function, so we also need to ensure that the SCTLR write has taken effect. This patch adds ISB instructions around the SCTLR write to ensure the visibility of the above. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-11-10ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.SCatalin Marinas
This patch modifies the proc-v7.S file so that it only contains code shared between classic MMU and LPAE. The non-common code is factored out into a separate file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-11-10ARM: LPAE: Move the FSR definitions to separate filesCatalin Marinas
The FSR structure is different with LPAE and this patch moves the classic MMU specific definition to a separate fsr-2level.c file that is included in fault.c. It also moves the fsr_fs and FSR bits to the fault.h file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-11-10ARM: LPAE: Move page table maintenance macros to pgtable-2level.hCatalin Marinas
The page table maintenance macros need to be duplicated between the classic and the LPAE MMU so this patch moves those that are not common to the pgtable-2level.h file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-11-10ARM: pgtable: Fix compiler warning in ioremap.c introduced by nopudCatalin Marinas
With the arch/arm code conversion to pgtable-nopud.h, the section and supersection (un|re)map code triggers compiler warnings on UP systems. This is caused by pmd_offset() being given a pgd_t argument rather than a pud_t one. This patch makes the necessary conversion with the assumption that the pud is folded into the pgd. The page table setting code only loops over the pmd which is enough with the classic page tables. This code is not compiled when LPAE is enabled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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