From e88a36ff013258e268749428fccdb760f5668722 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 16 Nov 2021 14:58:19 +0300 Subject: arm64: dts: qcom: sm8450-qrd: tighten voltage regulators Tighten voltage regulators constraints according to the attached WLAN needs. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index e58fc7399799..a02193518dee 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -63,13 +63,13 @@ vreg_s11b_0p95: smps11 { regulator-name = "vreg_s11b_0p95"; - regulator-min-microvolt = <848000>; + regulator-min-microvolt = <966000>; regulator-max-microvolt = <1104000>; }; vreg_s12b_1p25: smps12 { regulator-name = "vreg_s12b_1p25"; - regulator-min-microvolt = <1224000>; + regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1400000>; }; @@ -147,7 +147,7 @@ vreg_s1c_1p86: smps1 { regulator-name = "vreg_s1c_1p86"; - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <1900000>; regulator-max-microvolt = <2024000>; }; @@ -300,8 +300,8 @@ vreg_s2e_0p85: smps2 { regulator-name = "vreg_s2e_0p85"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1040000>; + regulator-min-microvolt = <1012000>; + regulator-max-microvolt = <1012000>; }; vreg_l1e_0p8: ldo1 { @@ -339,6 +339,12 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; + + vreg_l7e_2p8: ldo7 { + regulator-name = "vreg_l7e_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; }; }; -- cgit v1.2.3 From 114a0bfb6044876bd3a57058f651f500b08d17af Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 10 Feb 2022 12:13:57 +0530 Subject: kbuild: Don't report disabled nodes with duplicate addresses Duplicated unit address is okay if we have only one such node enabled. So, remove '-Wno-unique_unit_address' from DTC_FLAGS. This helps in reducing warnings in qcom dts from 6483 unique_unit_address 1108 simple_bus_reg 764 avoid_unnecessary_addr_size 712 unit_address_vs_reg 120 graph_child_address 32 unique_unit_address_if_enabled to: 277 simple_bus_reg 191 avoid_unnecessary_addr_size 178 unit_address_vs_reg 32 unique_unit_address_if_enabled 30 graph_child_address which would help people focus on the actual warnings and fix them. Suggested-by: Rob Herring Signed-off-by: Vinod Koul --- scripts/Makefile.lib | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 3aa384cec76b..cac8269abc21 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -334,7 +334,8 @@ quiet_cmd_gzip = GZIP $@ # DTC # --------------------------------------------------------------------------- DTC ?= $(objtree)/scripts/dtc/dtc -DTC_FLAGS += -Wno-interrupt_provider +DTC_FLAGS += -Wno-interrupt_provider \ + -Wno-unique_unit_address # Disable noisy checks by default ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),) @@ -342,8 +343,9 @@ DTC_FLAGS += -Wno-unit_address_vs_reg \ -Wno-avoid_unnecessary_addr_size \ -Wno-alias_paths \ -Wno-graph_child_address \ - -Wno-simple_bus_reg \ - -Wno-unique_unit_address + -Wno-simple_bus_reg +else +DTC_FLAGS += -Wunique_unit_address_if_enabled endif ifneq ($(findstring 2,$(KBUILD_EXTRA_WARN)),) -- cgit v1.2.3 From 6daae5451dae8678034b309e604dc5aa09a284a4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Feb 2022 06:21:11 +0300 Subject: arm64: dts: qcom: sm8450-qrd: add wcn6855 dt node Add device tree node describing WiFi/BT chip power semantics. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 40 +++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index a02193518dee..ad9b0f61eda9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -29,6 +29,24 @@ regulator-always-on; regulator-boot-on; }; + + wcn6856: wcn6856 { + compatible = "qcom,wcn6855"; + #power-domain-cells = <0>; + + vddaon-supply = <&vreg_s11b_0p95>; + vddcx-supply = <&vreg_s11b_0p95>; + vddmx-supply = <&vreg_s2e_0p85>; + vddrfa1-supply = <&vreg_s1c_1p86>; + vddrfa2-supply = <&vreg_s12b_1p25>; + vddio-supply = <&vreg_s10b_1p8>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_state &xo_clk_state>; + + xo-clk-gpios = <&tlmm 204 GPIO_ACTIVE_HIGH>; + wlan-en-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>; + }; }; &apps_rsc { @@ -408,6 +426,28 @@ &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; + + xo_clk_state: xo_clk_state { + pinconf { + pins = "gpio204"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-down; + }; + }; + + wlan_en_state: wlan_en_state { + pinconf { + pins = "gpio80"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-down; + }; + }; }; &uart7 { -- cgit v1.2.3 From d31ff8dd295a02119a6c1fecc07a12d9f175982a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Feb 2022 06:21:32 +0300 Subject: arm64: dts: qcom: sm8450-qrd: add bluetooth support Add QUP, UART and bluetooth device tree node to enable bluetooth on SM8450-QRD. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index ad9b0f61eda9..86f5f7a8c197 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -14,6 +14,7 @@ aliases { serial0 = &uart7; + serial1 = &uart20; }; chosen { @@ -392,6 +393,10 @@ status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &remoteproc_adsp { status = "okay"; firmware-name = "qcom/sm8450/adsp.mbn"; @@ -427,6 +432,17 @@ &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; + bt_en_state: bt-default-state { + bt-en { + pins = "gpio81"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-up; + }; + }; + xo_clk_state: xo_clk_state { pinconf { pins = "gpio204"; @@ -454,6 +470,18 @@ status = "okay"; }; +&uart20 { + status = "okay"; + bluetooth { + /* a little lie */ + compatible = "qcom,wcn6855-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_state>; + power-domains = <&wcn6856>; + enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + }; +}; + &ufs_mem_hc { status = "okay"; -- cgit v1.2.3 From d1723b72883105c8b67ab203895701735e217d5d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Feb 2022 06:07:34 +0300 Subject: HACK: arm64: dts: qcom: sm8450-qrd: enable WiFi Add wcn-controller power domain to the pcie0 PHY node as a way to power up the WiFI part before enabling the PCIe bus. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 86f5f7a8c197..021c54010258 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -369,12 +369,15 @@ &pcie0 { status = "okay"; + max-link-speed = <2>; }; &pcie0_phy { status = "okay"; vdda-phy-supply = <&vreg_l5b_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; + + power-domains = <&wcn6856>; }; &gpi_dma0 { -- cgit v1.2.3 From 6e7e64bdc06d3051fd299376ff38b5c22535569c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:30:19 +0300 Subject: dt-bindings: mfd: qcom-spmi-pmic: add pm8450 entry Add bindings for the PM8450 PMIC (qcom,pm8450). Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index 6a3e3ede1ede..c3fb98396cc1 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -54,6 +54,7 @@ properties: - qcom,pm8350 - qcom,pm8350b - qcom,pm8350c + - qcom,pm8450 - qcom,pm8841 - qcom,pm8909 - qcom,pm8916 -- cgit v1.2.3 From 2fdd17a7671f232a3c87f59e7b631b35d168bae5 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Feb 2022 06:05:44 +0300 Subject: arm64: dts: qcom: sm8450-hdk: add wcn6855 dt node Add device tree node describing WiFi/BT chip power semantics. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 44 +++++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 38ccd44620d0..33c4057447b8 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -29,6 +29,24 @@ regulator-always-on; regulator-boot-on; }; + + wcn6856: wcn6856 { + compatible = "qcom,wcn6855"; + #power-domain-cells = <0>; + + vddaon-supply = <&vreg_s11b_0p95>; + vddcx-supply = <&vreg_s11b_0p95>; + vddmx-supply = <&vreg_s2e_0p85>; + vddrfa1-supply = <&vreg_s1c_1p86>; + vddrfa2-supply = <&vreg_s12b_1p25>; + vddio-supply = <&vreg_s10b_1p8>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_state &xo_clk_state>; + + xo-clk-gpios = <&tlmm 204 GPIO_ACTIVE_HIGH>; + wlan-en-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>; + }; }; &apps_rsc { @@ -148,7 +166,7 @@ vreg_s1c_1p86: smps1 { regulator-name = "vreg_s1c_1p86"; - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <1900000>; regulator-max-microvolt = <2024000>; }; @@ -301,7 +319,7 @@ vreg_s2e_0p85: smps2 { regulator-name = "vreg_s2e_0p85"; - regulator-min-microvolt = <500000>; + regulator-min-microvolt = <1012000>; regulator-max-microvolt = <1040000>; }; @@ -396,6 +414,28 @@ &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; + + xo_clk_state: xo_clk_state { + pinconf { + pins = "gpio204"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-down; + }; + }; + + wlan_en_state: wlan_en_state { + pinconf { + pins = "gpio80"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-down; + }; + }; }; &uart7 { -- cgit v1.2.3 From ac17c5580376a151a5023ef849eae6b82df45dac Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Feb 2022 06:06:37 +0300 Subject: arm64: dts: qcom: sm8450-hdk: add bluetooth support Add QUP, UART and bluetooth device tree node to enable bluetooth on SM8450-HDK. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 33c4057447b8..5fd0cd2a057c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -14,6 +14,7 @@ aliases { serial0 = &uart7; + serial1 = &uart20; }; chosen { @@ -412,9 +413,24 @@ status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; + bt_en_state: bt-default-state { + bt-en { + pins = "gpio81"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-up; + }; + }; + xo_clk_state: xo_clk_state { pinconf { pins = "gpio204"; @@ -442,6 +458,18 @@ status = "okay"; }; +&uart20 { + status = "okay"; + bluetooth { + /* a little lie */ + compatible = "qcom,wcn6855-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_state>; + power-domains = <&wcn6856>; + enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + }; +}; + &ufs_mem_hc { status = "okay"; -- cgit v1.2.3 From 0415c106a150acdb3ba7ee7a6a171cafd0e7dd7a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Feb 2022 06:07:34 +0300 Subject: HACK: arm64: dts: qcom: sm8450-hdk: enable WiFi Add wcn-controller power domain to the pcie0 PHY node as a way to power up the WiFI part before enabling the PCIe bus. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 5fd0cd2a057c..e464bc72d1a5 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -377,6 +377,8 @@ status = "okay"; vdda-phy-supply = <&vreg_l5b_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; + + power-domains = <&wcn6856>; }; &pcie1 { -- cgit v1.2.3 From 573ed4c875e2d50296aeca96e43e93439879bf65 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 11 Apr 2022 15:34:17 +0300 Subject: arm64: dts: qcom: sm8450: provide additional MSI interrupts On SM8450 each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe0 host. Tested on Qualcomm RB5 platform with first group of MSI interrupts being used by the PME and attached ath11k WiFi chip using second group of MSI interrupts. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d32f08df743d..36f6067f03c2 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1729,8 +1729,15 @@ ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "msi8"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ -- cgit v1.2.3 From 85e0f721d71a2e75a809637abd914bd7133e40f4 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Wed, 11 May 2022 18:46:53 +0530 Subject: arm64: dts: qcom: Add power-domains property for apps_rsc Add power-domains property which allows apps_rsc device to attach to cluster power domain on sm8150, sm8250, sm8350 and sm8450. Cc: devicetree@vger.kernel.org Signed-off-by: Maulik Shah Reviewed-by: Ulf Hansson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index cef8c4f4f0ff..ecaae6f5ee6b 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -4010,6 +4010,7 @@ , , ; + power-domains = <&CLUSTER_PD>; rpmhcc: clock-controller { compatible = "qcom,sm8150-rpmh-clk"; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index a5b62cadb129..c32227ea40f9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4955,6 +4955,7 @@ qcom,drv-id = <2>; qcom,tcs-config = , , , ; + power-domains = <&CLUSTER_PD>; rpmhcc: clock-controller { compatible = "qcom,sm8250-rpmh-clk"; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a86d9ea93b9d..b5d036d72059 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2004,6 +2004,7 @@ qcom,drv-id = <2>; qcom,tcs-config = , , , ; + power-domains = <&CLUSTER_PD>; rpmhcc: clock-controller { compatible = "qcom,sm8350-rpmh-clk"; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 36f6067f03c2..cf8c3d1645c4 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3006,6 +3006,7 @@ qcom,drv-id = <2>; qcom,tcs-config = , , , ; + power-domains = <&CLUSTER_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; -- cgit v1.2.3 From b9eb3fc0eea65a1235ed1cd5637bc1d5e4583394 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 17 Feb 2022 03:19:11 +0300 Subject: arm64: dts: qcom: sm8450: add RPMH_REGULATOR_LEVEL_LOW_SVS_D1 Add another power saving state used on SM8450. Unfortunately adding it in proper place causes renumbering of all the opp states in sm8450.dtsi Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++-------- include/dt-bindings/power/qcom-rpmpd.h | 1 + 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index cf8c3d1645c4..51e4b7fcaab4 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3035,35 +3035,39 @@ opp-level = ; }; - rpmhpd_opp_low_svs: opp3 { + rpmhpd_opp_low_svs_d1: opp3 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp4 { opp-level = ; }; - rpmhpd_opp_svs: opp4 { + rpmhpd_opp_svs: opp5 { opp-level = ; }; - rpmhpd_opp_svs_l1: opp5 { + rpmhpd_opp_svs_l1: opp6 { opp-level = ; }; - rpmhpd_opp_nom: opp6 { + rpmhpd_opp_nom: opp7 { opp-level = ; }; - rpmhpd_opp_nom_l1: opp7 { + rpmhpd_opp_nom_l1: opp8 { opp-level = ; }; - rpmhpd_opp_nom_l2: opp8 { + rpmhpd_opp_nom_l2: opp9 { opp-level = ; }; - rpmhpd_opp_turbo: opp9 { + rpmhpd_opp_turbo: opp10 { opp-level = ; }; - rpmhpd_opp_turbo_l1: opp10 { + rpmhpd_opp_turbo_l1: opp11 { opp-level = ; }; }; diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index f5f82dde7399..b9c707e35fba 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -158,6 +158,7 @@ /* SDM845 Power Domain performance levels */ #define RPMH_REGULATOR_LEVEL_RETENTION 16 #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 #define RPMH_REGULATOR_LEVEL_LOW_SVS 64 #define RPMH_REGULATOR_LEVEL_SVS 128 #define RPMH_REGULATOR_LEVEL_SVS_L0 144 -- cgit v1.2.3 From 1bcdb22f21baf910ca872cc48bbff7ed8bd44fa2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 17 Feb 2022 03:27:53 +0300 Subject: arm64: dts: qcom: sm8450: add display hardware devices Add devices tree nodes describing display hardware on SM8450: - Display Clock Controller - MDSS - MDP - two DSI controllers and DSI PHYs This does not provide support for DP controllers present on SM8450. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 314 +++++++++++++++++++++++++++++++++++ 1 file changed, 314 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 51e4b7fcaab4..9052a7c8e22f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -2329,6 +2330,319 @@ status = "disabled"; }; + mdss: mdss@ae00000 { + compatible = "qcom,sm8450-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + /* same path used twice */ + interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, + <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x2800 0x402>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + + }; + + mdp_opp_table: mdp-opp-table { + compatible = "operating-points-v2"; + + opp-172000000 { + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + + dsi_opp_table: dsi-opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8450-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&dsi0_phy 0>, <&dsi0_phy 1>, + <&dsi1_phy 0>, <&dsi1_phy 1>, + <0>, <0>, + <0>, <0>, + <0>, <0>, + <0>, <0>, + <&sleep_clk>; + clock-names = "iface", + "bi_tcxo", + "bi_tcxo_ao", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp0_phy_pll_link_clk", + "dp0_phy_pll_vco_div_clk", + "dp1_phy_pll_link_clk", + "dp1_phy_pll_vco_div_clk", + "dp2_phy_pll_link_clk", + "dp2_phy_pll_vco_div_clk", + "dp3_phy_pll_link_clk", + "dp3_phy_pll_vco_div_clk", + "sleep_clk"; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + status = "disabled"; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8450-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; -- cgit v1.2.3 From 05261b7e3a6731aa6c0ea273eb1de8db41d4e40d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 25 Apr 2022 12:33:56 +0300 Subject: arm64: dts: qcom: sm8450-hdk: enable display hardware Enable MDSS/DPU/DSI0 on SM8450-HDK device. Note, there is no panel configuration (yet). Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index e464bc72d1a5..5fcd20efbe77 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -512,3 +512,21 @@ vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p91>; }; + +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + vdda-supply = <&vreg_l6b_1p2>; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l5b_0p88>; +}; -- cgit v1.2.3 From 3d156ef8e637609a3d116c9aed74d47c0e19bd01 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 1 Dec 2021 12:59:11 +0530 Subject: arm64: dts: qcom: sm8450: add spmi node Add the spmi bus as found in the SM8450 SoC Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Vladimir Zapolskiy --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9052a7c8e22f..05e264b7fa9d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2694,6 +2694,24 @@ #mbox-cells = <2>; }; + spmi_bus: spmi@c42d000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x00003000>, + <0x0 0x0c500000 0x0 0x00400000>, + <0x0 0x0c440000 0x0 0x00080000>, + <0x0 0x0c4c0000 0x0 0x00010000>, + <0x0 0x0c42d000 0x0 0x00010000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,sm8450-tlmm"; reg = <0 0x0f100000 0 0x300000>; -- cgit v1.2.3 From 3c0fe14778a22da9c19eceaafe3f7c9934c929a5 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 09:24:18 +0530 Subject: arm64: dts: qcom: sm8450-qrd: add pmic files SM8450 QRD features bunch of PMICs, add the PMICs which we have already upstream files Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 021c54010258..3a7c378d797b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -7,6 +7,9 @@ #include #include "sm8450.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pmr735b.dtsi" / { model = "Qualcomm Technologies, Inc. SM8450 QRD"; -- cgit v1.2.3 From 313cb4c7dfe9904c24e61b955b8eb3edb04c1f41 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 09:24:18 +0530 Subject: arm64: dts: qcom: sm8450-hdk: add pmic files SM8450 HDK features bunch of PMICs, add the PMICs which we have already upstream files Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 5fcd20efbe77..6315fb0ab219 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -7,6 +7,9 @@ #include #include "sm8450.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pmr735b.dtsi" / { model = "Qualcomm Technologies, Inc. SM8450 HDK"; -- cgit v1.2.3 From 41aa3bb869528933fcdd0680655ece8cda9d8499 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:31:32 +0300 Subject: arm64: dts: qcom: sm8450-qrd: add missing PMIC includes Add includes for PMICs used on the SM8450-HDK. This makes GPIO blocks and thermal sensors available to the user of the platform. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 3a7c378d797b..017bc48430ba 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -9,6 +9,10 @@ #include "sm8450.dtsi" #include "pm8350.dtsi" #include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pm8450.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" #include "pmr735b.dtsi" / { -- cgit v1.2.3 From 5f9091cdb5a5303e29ca220fa388f145d66c0d2a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:31:32 +0300 Subject: arm64: dts: qcom: sm8450-hdk: add missing PMIC includes Add includes for PMICs used on the SM8450-HDK. This makes GPIO blocks and thermal sensors available to the user of the platform. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 6315fb0ab219..2dacae1293f5 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -9,6 +9,10 @@ #include "sm8450.dtsi" #include "pm8350.dtsi" #include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pm8450.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" #include "pmr735b.dtsi" / { -- cgit v1.2.3