arm64: dts: qcom: msm8938: add support for CPR

Signed-off-by: Fabien Parent <fabien.parent@linaro.org>

1 files changed, 484 insertions, 12 deletions

diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi
index 433ad156a82d..effc13080bd6 100644
--- a/arch/arm64/boot/dts/qcom/msm8939.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi
@@ -46,7 +46,8 @@
 			enable-method = "spin-table";
 			reg = <0x100>;
 			next-level-cache = <&L2_1>;
-			power-domains = <&vreg_dummy>;
+			operating-points-v2 = <&cluster1_opp_table>;
+			power-domains = <&cpr>;
 			power-domain-names = "cpr";
 			qcom,acc = <&acc0>;
 			qcom,saw = <&saw0>;
@@ -65,7 +66,8 @@
 			enable-method = "spin-table";
 			reg = <0x101>;
 			next-level-cache = <&L2_1>;
-			power-domains = <&vreg_dummy>;
+			operating-points-v2 = <&cluster1_opp_table>;
+			power-domains = <&cpr>;
 			power-domain-names = "cpr";
 			qcom,acc = <&acc1>;
 			qcom,saw = <&saw1>;
@@ -79,7 +81,8 @@
 			enable-method = "spin-table";
 			reg = <0x102>;
 			next-level-cache = <&L2_1>;
-			power-domains = <&vreg_dummy>;
+			operating-points-v2 = <&cluster1_opp_table>;
+			power-domains = <&cpr>;
 			power-domain-names = "cpr";
 			qcom,acc = <&acc2>;
 			qcom,saw = <&saw2>;
@@ -93,7 +96,8 @@
 			enable-method = "spin-table";
 			reg = <0x103>;
 			next-level-cache = <&L2_1>;
-			power-domains = <&vreg_dummy>;
+			operating-points-v2 = <&cluster1_opp_table>;
+			power-domains = <&cpr>;
 			power-domain-names = "cpr";
 			qcom,acc = <&acc3>;
 			qcom,saw = <&saw3>;
@@ -111,7 +115,8 @@
 			clocks = <&apcs0_mbox>;
 			#cooling-cells = <2>;
 			next-level-cache = <&L2_0>;
-			power-domains = <&vreg_dummy>;
+			operating-points-v2 = <&cluster0_opp_table>;
+			power-domains = <&cpr>;
 			power-domain-names = "cpr";
 			L2_0: l2-cache@0 {
 				compatible = "cache";
@@ -125,7 +130,8 @@
 			enable-method = "spin-table";
 			reg = <0x1>;
 			next-level-cache = <&L2_0>;
-			power-domains = <&vreg_dummy>;
+			operating-points-v2 = <&cluster0_opp_table>;
+			power-domains = <&cpr>;
 			power-domain-names = "cpr";
 			qcom,acc = <&acc5>;
 			qcom,saw = <&saw5>;
@@ -139,7 +145,8 @@
 			enable-method = "spin-table";
 			reg = <0x2>;
 			next-level-cache = <&L2_0>;
-			power-domains = <&vreg_dummy>;
+			operating-points-v2 = <&cluster0_opp_table>;
+			power-domains = <&cpr>;
 			power-domain-names = "cpr";
 			qcom,acc = <&acc6>;
 			qcom,saw = <&saw6>;
@@ -153,7 +160,8 @@
 			enable-method = "spin-table";
 			reg = <0x3>;
 			next-level-cache = <&L2_0>;
-			power-domains = <&vreg_dummy>;
+			operating-points-v2 = <&cluster0_opp_table>;
+			power-domains = <&cpr>;
 			power-domain-names = "cpr";
 			qcom,acc = <&acc7>;
 			qcom,saw = <&saw7>;
@@ -423,6 +431,10 @@
 				reg = <0xd8 0x8>;
 				bits = <6 12>;
 			};
+			cpr_efuse_mem_acc: cpr_efuse_mem_acc@3 {
+				reg = <0x3 0x1>;
+				bits = <6 1>;
+			};
 			cpr_efuse_ring1: ring1@de {
 				reg = <0xde 0x4>;
 				bits = <6 3>;
@@ -455,6 +467,10 @@
 				reg = <0xc 0x1>;
 				bits = <2 3>;
 			};
+			cpr_efuse_speedbin_pvs: speedbin_pvs@0 {
+				reg = <0x0 0x10>;
+				bits = <0 127>;
+			};
 
 		};
 
@@ -1908,6 +1924,185 @@
 			#mbox-cells = <1>;
 		};
 
+		cpr: power-controller@b018000 {
+			compatible = "qcom,msm8939-cpr", "qcom,cpr";
+			reg = <0x0b018000 0x1000>;
+			interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&xo_board>;
+			clock-names = "ref";
+			power-domains = <&rpmpd MSM8939_VDDMX_AO>;
+			#power-domain-cells = <0>;
+			operating-points-v2 = <&cpr_opp_table>;
+			acc-syscon = <&tcsr>;
+
+			nvmem-cells = <&cpr_efuse_init_voltage1>,
+				<&cpr_efuse_init_voltage2>,
+				<&cpr_efuse_init_voltage3>,
+				<&cpr_efuse_quot1>,
+				<&cpr_efuse_quot2>,
+				<&cpr_efuse_quot3>,
+				<&cpr_efuse_ring1>,
+				<&cpr_efuse_ring2>,
+				<&cpr_efuse_ring3>,
+				<&cpr_efuse_revision>,
+				<&cpr_efuse_revision_high>,
+				<&cpr_efuse_pvs_version>,
+				<&cpr_efuse_pvs_version_high>,
+				<&cpr_efuse_speedbin>,
+				<&cpr_efuse_mem_acc>;
+			nvmem-cell-names = "cpr_init_voltage1",
+				"cpr_init_voltage2",
+				"cpr_init_voltage3",
+				"cpr_quotient1",
+				"cpr_quotient2",
+				"cpr_quotient3",
+				"cpr_ring_osc1",
+				"cpr_ring_osc2",
+				"cpr_ring_osc3",
+				"cpr_fuse_revision",
+				"cpr_fuse_revision_high",
+				"cpr_pvs_version",
+				"cpr_pvs_version_high",
+				"cpr_speedbin",
+				"cpr_mem_acc";
+			fuse-version-map =
+			/* map table to find the index for lookup table */
+			/* <Speed_bits PVS	CPR_Rev> */
+				<0	0	0>,
+				<0	0	1>,
+				<0	0	2>,
+				<0	0	3>,
+				<2	0	0>,
+				<2	0	1>,
+				<2	0	2>,
+				<2	0	3>,
+				<2	2	0>,
+				<2	2	1>,
+				<2	2	2>,
+				<2	2	3>,
+				<5	6	0>,
+				<5	6	1>,
+				<5	6	2>,
+				<5	6	3>,
+				<(-1)	(-1)	0>,
+				<(-1)	(-1)	1>,
+				<(-1)	(-1)	2>,
+				<(-1)	(-1)	3>;
+			init-voltage-adjustment =
+			/* table to lookup with index from matching map above */
+				<0 50000 0>,
+				<0 20000 0>,
+				<0 50000 0>,
+				<0 20000 0>,
+				<0 50000 0>,
+				<0 20000 0>,
+				<0 50000 0>,
+				<0 20000 0>,
+				<0 50000 0>,
+				<0 20000 0>,
+				<0 50000 0>,
+				<0 20000 0>,
+				<0 50000 0>,
+				<0 20000 0>,
+				<0 50000 0>,
+				<0 20000 0>,
+				<0 50000 0>,
+				<0 20000 0>,
+				<0 50000 0>,
+				<0 20000 0>;
+			quotient-adjustment =
+			/* table to lookup with index from matching map above */
+				<0  104   (-41)>, /* NOM + 50mv, TURBO - 20mv */
+				<0   41   (-41)>, /* NOM + 20mv, TURBO - 20mv */
+				<0  104   (-41)>, /* NOM + 50mv, TURBO - 20mv */
+				<0   41   (-41)>, /* NOM + 20mv, TURBO - 20mv */
+				<0  104   (-41)>, /* NOM + 50mv, TURBO - 20mv */
+				<0   41   (-41)>, /* NOM + 20mv, TURBO - 20mv */
+				<0  104   (-41)>, /* NOM + 50mv, TURBO - 20mv */
+				<0   41   (-41)>, /* NOM + 20mv, TURBO - 20mv */
+				<0   41  (-124)>, /* NOM + 20mv, TURBO - 60mv */
+				<0 (-20) (-124)>, /* NOM - 10mv, TURBO - 60mv */
+				<0  104  (-124)>, /* NOM + 50mv, TURBO - 60mv */
+				<0   41  (-124)>, /* NOM + 20mv, TURBO - 60mv */
+				<0   41   (-41)>, /* NOM + 20mv, TURBO - 20mv */
+				<0 (-20)  (-41)>, /* NOM - 10mv, TURBO - 20mv */
+				<0  104   (-41)>, /* NOM + 50mv, TURBO - 20mv */
+				<0   41   (-41)>, /* NOM + 20mv, TURBO - 20mv */
+				<0  104   (-41)>, /* NOM + 50mv, TURBO - 20mv */
+				<0   41   (-41)>, /* NOM + 20mv, TURBO - 20mv */
+				<0  104   (-41)>, /* NOM + 50mv, TURBO - 20mv */
+				<0   41   (-41)>; /* NOM + 20mv, TURBO - 20mv */
+			/* quot adjustment for frequencies in cpr_opp_table */
+			virtual-corner-quotient-adjustment =
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-104) (-41) 0 0 0 0 0 0 0 0 0 0
+				 113 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-41) (-41) 0 0 0 0 0 0 0 0 0 0
+				 113 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-104) (-41) 0 0 0 0 0 0 0 0 0 0
+				 113 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-41) (-41) 0 0 0 0 0 0 0 0 0 0
+				 113 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-104) (-41) 0 0 0 0 0 0 0 0 0 0
+				 113 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-41) (-41) 0 0 0 0 0 0 0 0 0 0
+				 113 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-104) (-41) 0 0 0 0 0 0 0 0 0 0
+				 113 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-41) (-41) 0 0 0 0 0 0 0 0 0 0
+				 113 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-104) (-41) 0 0 0 0 0 0 0 0 0 0
+				 196 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-41) (-41) 0 0 0 0 0 0 0 0 0 0
+				 196 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-104) (-41) 0 0 0 0 0 0 0 0 0 0
+				 196 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-41) (-41) 0 0 0 0 0 0 0 0 0 0
+				 196 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-104) (-41) 0 0 0 0 0 0 0 0 0 0
+				 0 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-41) (-41) 0 0 0 0 0 0 0 0 0 0 0
+				 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-104) (-41) 0 0 0 0 0 0 0 0 0 0
+				 0 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-41) (-41) 0 0 0 0 0 0 0 0 0 0 0
+				 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-104) (-41) 0 0 0 0 0 0 0 0 0 0
+				 0 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-41) (-41) 0 0 0 0 0 0 0 0 0 0 0
+				 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-104) (-41) 0 0 0 0 0 0 0 0 0 0
+				 0 0 0 0 0>,
+				<0 0 0 (-104) (-104) (-104) (-104) (-104) (-104)
+				 (-104) (-104) (-41) (-41) 0 0 0 0 0 0 0 0 0 0 0
+				 0 0 0 0>;
+
+			voltage-floor-override =
+				<1050000 1050000 1050000 1050000 1050000 1050000
+				 1050000 1050000 1050000 1050000 1050000 1050000
+				 1050000 1100000 1137500 1137500 1137500 1137500
+				 1137500 1137500 1137500 1137500 1137500 1137500
+				 1137500 1137500 1137500 1137500>;
+		};
+
 		a53pll_c1: clock@b016000 {
 			compatible = "qcom,msm8939-a53pll";
 			reg = <0x0b016000 0x40>;
@@ -2402,10 +2597,6 @@
 			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
-	vreg_dummy: regulator-dummy {
-		#power-domain-cells = <0>;
-	};
-
 	wcnss-smp2p {
 		compatible = "qcom,smp2p";
 		qcom,smem = <451>, <431>;
@@ -2430,4 +2621,285 @@
 			#interrupt-cells = <2>;
 		};
 	};
+
+	cluster0_opp_table: cluster0-opp-table {
+		compatible = "operating-points-v2-kryo-cpu";
+		opp-shared;
+
+		/* Used by qcom-cpufreq-nvmem.c */
+		nvmem-cells = <&cpr_efuse_speedbin_pvs>;
+		nvmem-cell-names = "cpr_efuse_speedbin_pvs";
+
+		/*
+		 * Bitmap for "opp-supported-hw":
+		 * speed0-bin-v0: 0x1
+		 * speed2-bin-v0: 0x2
+		 * speed2-bin-v2: 0x4
+		 * speed4-bin-v0: 0x8
+		 * speed5-bin-v0: 0x10
+		 * speed5-bin-v6: 0x20
+		 * otherwise:     0x1
+		 */
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp3>;
+		};
+
+		opp-249600000 {
+			opp-hz = /bits/ 64 <249600000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp3>;
+		};
+
+		opp-499200000 {
+			opp-hz = /bits/ 64 <499200000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp9>;
+		};
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp12>;
+		};
+
+		opp-998400000 {
+			opp-hz = /bits/ 64 <998400000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp17>;
+		};
+
+		opp-1113600000 {
+			opp-hz = /bits/ 64 <1113600000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp24>;
+		};
+	};
+
+	cluster1_opp_table: cluster1-opp-table {
+		compatible = "operating-points-v2-kryo-cpu";
+		opp-shared;
+
+		/* Used by qcom-cpufreq-nvmem.c */
+		nvmem-cells = <&cpr_efuse_speedbin_pvs>;
+		nvmem-cell-names = "cpr_efuse_speedbin_pvs";
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp3>;
+		};
+
+		opp-345600000 {
+			opp-hz = /bits/ 64 <345600000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp3>;
+		};
+
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp3>;
+		};
+
+		opp-533330000 {
+			opp-hz = /bits/ 64 <533330000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp9>;
+		};
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp9>;
+		};
+
+		opp-960000000 {
+			opp-hz = /bits/ 64 <960000000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp12>;
+		};
+
+		opp-1113600000 {
+			opp-hz = /bits/ 64 <1113600000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp14>;
+		};
+
+		opp-1344000000 {
+			opp-hz = /bits/ 64 <1344000000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp17>;
+		};
+
+		opp-1459200000 {
+			opp-hz = /bits/ 64 <1459200000>;
+			opp-supported-hw = <0x3f>;
+			required-opps = <&cpr_opp20>;
+		};
+
+		opp-1497600000 {
+			opp-hz = /bits/ 64 <1497600000>;
+			opp-supported-hw = <0x3b>;
+			required-opps = <&cpr_opp21>;
+		};
+
+		opp-1651200000 {
+			opp-hz = /bits/ 64 <1651200000>;
+			opp-supported-hw = <0x38>;
+			required-opps = <&cpr_opp26>;
+		};
+	};
+
+
+	/* Frequencies in below opp is for cpr_opp virtual corner calculation,
+	 * not strictly coupled with frquencies in CPU opp for CPUs may require
+	 * different cpr_opp for specific frquency.
+	 */
+	cpr_opp_table: cpr-opp-table {
+		compatible = "operating-points-v2-qcom-level";
+
+		cpr_opp1: opp1 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-level = <1>;
+			qcom,opp-fuse-level = <1>;
+		};
+		cpr_opp2: opp2 {
+			opp-hz = /bits/ 64 <345600000>;
+			opp-level = <2>;
+			qcom,opp-fuse-level = <1>;
+		};
+		cpr_opp3: opp3 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-level = <3>;
+			qcom,opp-fuse-level = <1>;
+		};
+		cpr_opp4: opp4 {
+			opp-hz = /bits/ 64 <422400000>;
+			opp-level = <4>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp5: opp5 {
+			opp-hz = /bits/ 64 <499200000>;
+			opp-level = <5>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp6: opp6 {
+			opp-hz = /bits/ 64 <533330000>;
+			opp-level = <6>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp7: opp7 {
+			opp-hz = /bits/ 64 <652800000>;
+			opp-level = <7>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp8: opp8 {
+			opp-hz = /bits/ 64 <729600000>;
+			opp-level = <8>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp9: opp9 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-level = <9>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp10: opp10 {
+			opp-hz = /bits/ 64 <806400000>;
+			opp-level = <10>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp11: opp11 {
+			opp-hz = /bits/ 64 <883200000>;
+			opp-level = <11>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp12: opp12 {
+			opp-hz = /bits/ 64 <960000000>;
+			opp-level = <12>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp13: opp13 {
+			opp-hz = /bits/ 64 <1036800000>;
+			opp-level = <13>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp14: opp14 {
+			opp-hz = /bits/ 64 <1113600000>;
+			opp-level = <14>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp15: opp15 {
+			opp-hz = /bits/ 64 <1190400000>;
+			opp-level = <15>;
+			qcom,opp-fuse-level = <3>;
+		};
+		cpr_opp16: opp16 {
+			opp-hz = /bits/ 64 <1267200000>;
+			opp-level = <16>;
+			qcom,opp-fuse-level = <3>;
+		};
+		cpr_opp17: opp17 {
+			opp-hz = /bits/ 64 <1344000000>;
+			opp-level = <17>;
+			qcom,opp-fuse-level = <3>;
+		};
+		cpr_opp18: opp18 {
+			opp-hz = /bits/ 64 <1363200000>;
+			opp-level = <18>;
+			qcom,opp-fuse-level = <3>;
+		};
+		cpr_opp19: opp19 {
+			opp-hz = /bits/ 64 <1420800000>;
+			opp-level = <19>;
+			qcom,opp-fuse-level = <3>;
+		};
+		cpr_opp20: opp20 {
+			opp-hz = /bits/ 64 <1459200000>;
+			opp-level = <20>;
+			qcom,opp-fuse-level = <3>;
+		};
+		cpr_opp21: opp21 {
+			opp-hz = /bits/ 64 <1497600000>;
+			opp-level = <21>;
+			qcom,opp-fuse-level = <3>;
+		};
+		cpr_opp22: opp22 {
+			opp-hz = /bits/ 64 <1536000000>;
+			opp-level = <22>;
+			qcom,opp-fuse-level = <3>;
+		};
+		cpr_opp23: opp23 {
+			opp-hz = /bits/ 64 <1574400000>;
+			opp-level = <23>;
+			qcom,opp-fuse-level = <3>;
+		};
+		cpr_opp24: opp24 {
+			opp-hz = /bits/ 64 <1612800000>;
+			opp-level = <24>;
+			qcom,opp-fuse-level = <3>;
+		};
+		cpr_opp25: opp25 {
+			opp-hz = /bits/ 64 <1632000000>;
+			opp-level = <25>;
+			qcom,opp-fuse-level = <3>;
+		};
+		cpr_opp26: opp26 {
+			opp-hz = /bits/ 64 <1651200000>;
+			opp-level = <26>;
+			qcom,opp-fuse-level = <3>;
+		};
+		cpr_opp27: opp27 {
+			opp-hz = /bits/ 64 <1689600000>;
+			opp-level = <27>;
+			qcom,opp-fuse-level = <3>;
+		};
+		cpr_opp28: opp28 {
+			opp-hz = /bits/ 64 <1708800000>;
+			opp-level = <28>;
+			qcom,opp-fuse-level = <3>;
+		};
+	};
+
 };